soc: aspeed: Workaround for AST2700 vGPIO int sts

In AST2700, the vGPIO event and System event 1 are reversed in the
ESPI_CH1_INT_STS register. Refer to following bit definition for the
meaning of each bit in the ESPI_CH1_INT_STS register:

Read ESPI_CH1_INT_STS:
  bit0: System event
  bit1: vGPIO event
  bit2: System event 1
  bit3: vGP50 event

Write ESPI_CH1_INT_STS:
  bit0: Clear System event
  bit1: Clear System event 1
  bit2: Clear vGPIO event
  bit3: Clear vGP50 event

This patch adds a workaround to read bit1 for determining vGPIO int and
clear the vGPIO event interrupt status via bit2 in the ESPI_CH1_INT_STS
register.

refs: https://github.com/AspeedTech-BMC/linux/commit/0283c3bb2c33a0cf868c05214068dfa57fc44eb2

Signed-off-by: YunHsuanChung <yh_chung@aspeedtech.com>
Change-Id: Ie6211f571d0e26f7f00917977ab5fa6780ea7190