)]}'
{
  "commit": "7fbb6f1b3cd0a979775976c5ecd0a6dd98466ada",
  "tree": "b742e47408410af585503a9050f7e1f679258cc2",
  "parents": [
    "d503974e602724d1040331e1c0ed7529ff570c73"
  ],
  "author": {
    "name": "Jake Chiang",
    "email": "hung-tse.chiang@fii-na.corp-partner.google.com",
    "time": "Thu Aug 13 13:35:03 2026 +0800"
  },
  "committer": {
    "name": "mdb:gbmc-git-owners",
    "email": "superproject-auto-update@invalid",
    "time": "Sun Aug 16 17:42:52 2026 -0700"
  },
  "message": "kernel: SRCREV bump 15e3ed4..dd52df9\n\nBilly Tsai (2):\n    arm64: dts: aspeed: reserve per-instance DMA pools for i3c HCI\n    i3c: mipi-i3c-hci: bind DMA rings to the reserved-memory pool\n\nJake Chiang (2):\n    arm64: dts: aspeed: adjust I3C HCI reserved memory layout\n    i3c: mipi-i3c-hci: dma: allocate IBI data before IBI status\n\nTested: Built\n\nGoogle-Bug-Id: 542414147\nChange-Id: I75eebddeac6d30c6e242a85ab83d5869c76f1da0\nSigned-off-by: Jake Chiang \u003chung-tse.chiang@fii-na.corp-partner.google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "649e144242b127a1fca3298cbceaa60dc04fc40a",
      "old_mode": 57344,
      "old_path": "meta-gbmc-staging",
      "new_id": "42ecf7e48e6890ea5c6b4c5bdf954f0483ceecd9",
      "new_mode": 57344,
      "new_path": "meta-gbmc-staging"
    }
  ]
}