)]}'
{
  "commit": "afea7bb0c46f820798cd16be398e702df9fa4567",
  "tree": "6f76f5c97a6947ab223f7f13716839f7f1f2ee6d",
  "parents": [
    "d104fa70db9ab59b209f9c927230b8f10e41320e"
  ],
  "author": {
    "name": "Jake Chiang",
    "email": "hung-tse.chiang@fii-na.corp-partner.google.com",
    "time": "Tue Aug 11 14:45:29 2026 +0800"
  },
  "committer": {
    "name": "mdb:gbmc-git-owners",
    "email": "superproject-auto-update@invalid",
    "time": "Wed Aug 12 20:38:36 2026 -0700"
  },
  "message": "i3c: mipi-i3c-hci: dma: allocate IBI data before IBI status\n\nThe coherent DMA pool allocator is page-based and uses\nbitmap_find_free_region(). An allocation of 2^order pages must start\nat an offset aligned to 2^order pages.\n\nThe IBI data ring requires two pages (order 1), so it must start at a\ntwo-page aligned offset. Allocating the one-page IBI status ring first\nleaves the next free page unaligned for the two-page IBI data ring.\n\nAllocate the IBI data ring before the IBI status ring to avoid the\nalignment hole and allow the DMA buffers to fit in the 20 KiB\nreserved-memory region.\n\nTested:\n```\nThe platform DTS was not modified for this test.\nLTPI I3C and I3C hub initialization logs were omitted for clarity,\nas they are unrelated to the I3C DMA reserved-memory changes.\n\ndmesg:\nroot@:~# dmesg | grep i3c\n[    0.000000] OF: reserved mem: initialized node i3c0-reserved@431c00000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c00000..0x0000000431c04fff (20 KiB) nomap non-reusable i3c0-reserved@431c00000\n[    0.000000] OF: reserved mem: initialized node i3c1-reserved@431c05000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c05000..0x0000000431c09fff (20 KiB) nomap non-reusable i3c1-reserved@431c05000\n[    0.000000] OF: reserved mem: initialized node i3c2-reserved@431c0a000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c0a000..0x0000000431c0efff (20 KiB) nomap non-reusable i3c2-reserved@431c0a000\n[    0.000000] OF: reserved mem: initialized node i3c3-reserved@431c0f000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c0f000..0x0000000431c13fff (20 KiB) nomap non-reusable i3c3-reserved@431c0f000\n[    0.000000] OF: reserved mem: initialized node i3c4-reserved@431c14000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c14000..0x0000000431c18fff (20 KiB) nomap non-reusable i3c4-reserved@431c14000\n[    0.000000] OF: reserved mem: initialized node i3c5-reserved@431c19000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c19000..0x0000000431c1dfff (20 KiB) nomap non-reusable i3c5-reserved@431c19000\n[    0.000000] OF: reserved mem: initialized node i3c6-reserved@431c1e000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c1e000..0x0000000431c22fff (20 KiB) nomap non-reusable i3c6-reserved@431c1e000\n[    0.000000] OF: reserved mem: initialized node i3c7-reserved@431c23000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c23000..0x0000000431c27fff (20 KiB) nomap non-reusable i3c7-reserved@431c23000\n[    0.000000] OF: reserved mem: initialized node i3c8-reserved@431c28000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c28000..0x0000000431c2cfff (20 KiB) nomap non-reusable i3c8-reserved@431c28000\n[    0.000000] OF: reserved mem: initialized node i3c9-reserved@431c2d000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c2d000..0x0000000431c31fff (20 KiB) nomap non-reusable i3c9-reserved@431c2d000\n[    0.000000] OF: reserved mem: initialized node i3c10-reserved@431c32000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c32000..0x0000000431c36fff (20 KiB) nomap non-reusable i3c10-reserved@431c32000\n[    0.000000] OF: reserved mem: initialized node i3c11-reserved@431c37000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c37000..0x0000000431c3bfff (20 KiB) nomap non-reusable i3c11-reserved@431c37000\n[    0.000000] OF: reserved mem: initialized node i3c12-reserved@431c3c000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c3c000..0x0000000431c40fff (20 KiB) nomap non-reusable i3c12-reserved@431c3c000\n[    0.000000] OF: reserved mem: initialized node i3c13-reserved@431c41000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c41000..0x0000000431c45fff (20 KiB) nomap non-reusable i3c13-reserved@431c41000\n[    0.000000] OF: reserved mem: initialized node i3c14-reserved@431c46000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c46000..0x0000000431c4afff (20 KiB) nomap non-reusable i3c14-reserved@431c46000\n[    0.000000] OF: reserved mem: initialized node i3c15-reserved@431c4b000, compatible id shared-dma-pool\n[    0.000000] OF: reserved mem: 0x0000000431c4b000..0x0000000431c4ffff (20 KiB) nomap non-reusable i3c15-reserved@431c4b000\n.\n.\n.\n[    5.678843]  14c26000.i3c6: MIPI I3C HCI v1.1 r00\n[    5.684122]  14c26000.i3c6: DAT: 127 8-bytes entries at offset 0x100\n[    5.691223]  14c26000.i3c6: DCT: 1 16-bytes entries at offset 0x500\n[    5.698226]  14c26000.i3c6: Ring Headers at offset 0x800\n[    5.704166]  14c26000.i3c6: PIO section at offset 0xd0\n[    5.709905]  14c26000.i3c6: Extended Caps at offset 0xf00\n[    5.715942]  14c26000.i3c6: vendor MIPI ID: 0x3f6\n[    5.721205]  14c26000.i3c6: vendor version ID: 0x2\n[    5.726559]  14c26000.i3c6: vendor product ID: 0x6020003\n[    5.726566]  14c26000.i3c6: operation mode: primary/secondary master\n[    5.747743]  14c26000.i3c6: INHOUSE control at offset 0xd00\n[    5.753967]  14c26000.i3c6: PHY control at offset 0xe00\n[    5.759821]  14c26000.i3c6: Using DMA\n[    5.764180] i3c 14c26000.i3c6: Master Mode\n[    5.768772] i3c 14c26000.i3c6: core rate \u003d 250000000 core period \u003d 4 ns\n[    5.776191] i3c 14c26000.i3c6: 1 DMA rings available\n[    5.781813] mipi-i3c-hci 14c26000.i3c6: assigned reserved memory node i3c6-reserved@431c1e000\n[    5.791373] i3c 14c26000.i3c6: Ring 0 at offset 0x830\n[    5.797872]  14c27000.i3c7: MIPI I3C HCI v1.1 r00\n[    5.803157]  14c27000.i3c7: DAT: 127 8-bytes entries at offset 0x100\n[    5.810257]  14c27000.i3c7: DCT: 1 16-bytes entries at offset 0x500\n[    5.817267]  14c27000.i3c7: Ring Headers at offset 0x800\n[    5.823210]  14c27000.i3c7: PIO section at offset 0xd0\n[    5.828951]  14c27000.i3c7: Extended Caps at offset 0xf00\n[    5.834994]  14c27000.i3c7: vendor MIPI ID: 0x3f6\n[    5.840248]  14c27000.i3c7: vendor version ID: 0x2\n[    5.840253]  14c27000.i3c7: vendor product ID: 0x6020003\n[    5.840259]  14c27000.i3c7: operation mode: primary/secondary master\n[    5.855123]  14c27000.i3c7: INHOUSE control at offset 0xd00\n[    5.868145]  14c27000.i3c7: PHY control at offset 0xe00\n[    5.882747]  14c27000.i3c7: Using DMA\n[    5.910813] i3c 14c27000.i3c7: Master Mode\n[    5.915397] i3c 14c27000.i3c7: core rate \u003d 250000000 core period \u003d 4 ns\n[    5.922809] i3c 14c27000.i3c7: 1 DMA rings available\n[    5.928400] mipi-i3c-hci 14c27000.i3c7: assigned reserved memory node i3c7-reserved@431c23000\n[    5.937926] i3c 14c27000.i3c7: Ring 0 at offset 0x830\n[    5.944308]  14c2a000.i3c10: MIPI I3C HCI v1.1 r00\n[    5.949687]  14c2a000.i3c10: DAT: 127 8-bytes entries at offset 0x100\n[    5.956893]  14c2a000.i3c10: DCT: 1 16-bytes entries at offset 0x500\n[    5.963995]  14c2a000.i3c10: Ring Headers at offset 0x800\n[    5.970025]  14c2a000.i3c10: PIO section at offset 0xd0\n[    5.975866]  14c2a000.i3c10: Extended Caps at offset 0xf00\n[    5.981994]  14c2a000.i3c10: vendor MIPI ID: 0x3f6\n[    5.987350]  14c2a000.i3c10: vendor version ID: 0x2\n[    5.992799]  14c2a000.i3c10: vendor product ID: 0x6020003\n[    5.998834]  14c2a000.i3c10: operation mode: primary/secondary master\n[    6.006022]  14c2a000.i3c10: INHOUSE control at offset 0xd00\n[    6.012347]  14c2a000.i3c10: PHY control at offset 0xe00\n[    6.018318]  14c2a000.i3c10: Using DMA\n[    6.022705] i3c 14c2a000.i3c10: Master Mode\n[    6.027382] i3c 14c2a000.i3c10: core rate \u003d 250000000 core period \u003d 4 ns\n[    6.034892] i3c 14c2a000.i3c10: 1 DMA rings available\n[    6.040569] mipi-i3c-hci 14c2a000.i3c10: assigned reserved memory node i3c10-reserved@431c32000\n[    6.050288] i3c 14c2a000.i3c10: Ring 0 at offset 0x830\n[    6.056793]  14c2b000.i3c11: MIPI I3C HCI v1.1 r00\n[    6.062168]  14c2b000.i3c11: DAT: 127 8-bytes entries at offset 0x100\n[    6.069373]  14c2b000.i3c11: DCT: 1 16-bytes entries at offset 0x500\n[    6.076475]  14c2b000.i3c11: Ring Headers at offset 0x800\n[    6.082506]  14c2b000.i3c11: PIO section at offset 0xd0\n[    6.088353]  14c2b000.i3c11: Extended Caps at offset 0xf00\n[    6.094483]  14c2b000.i3c11: vendor MIPI ID: 0x3f6\n[    6.099839]  14c2b000.i3c11: vendor version ID: 0x2\n[    6.105288]  14c2b000.i3c11: vendor product ID: 0x6020003\n[    6.111323]  14c2b000.i3c11: operation mode: primary/secondary master\n[    6.118509]  14c2b000.i3c11: INHOUSE control at offset 0xd00\n[    6.124834]  14c2b000.i3c11: PHY control at offset 0xe00\n[    6.130776]  14c2b000.i3c11: Using DMA\n[    6.135082] i3c 14c2b000.i3c11: Master Mode\n[    6.139765] i3c 14c2b000.i3c11: core rate \u003d 250000000 core period \u003d 4 ns\n[    6.147277] i3c 14c2b000.i3c11: 1 DMA rings available\n[    6.152954] mipi-i3c-hci 14c2b000.i3c11: assigned reserved memory node i3c11-reserved@431c37000\n[    6.162680] i3c 14c2b000.i3c11: Ring 0 at offset 0x830\n[    6.169054]  14c2c000.i3c12: MIPI I3C HCI v1.1 r00\n[    6.174415]  14c2c000.i3c12: DAT: 127 8-bytes entries at offset 0x100\n[    6.181622]  14c2c000.i3c12: DCT: 1 16-bytes entries at offset 0x500\n[    6.188725]  14c2c000.i3c12: Ring Headers at offset 0x800\n[    6.194759]  14c2c000.i3c12: PIO section at offset 0xd0\n[    6.200595]  14c2c000.i3c12: Extended Caps at offset 0xf00\n[    6.206727]  14c2c000.i3c12: vendor MIPI ID: 0x3f6\n[    6.212078]  14c2c000.i3c12: vendor version ID: 0x2\n[    6.217531]  14c2c000.i3c12: vendor product ID: 0x6020003\n[    6.223567]  14c2c000.i3c12: operation mode: primary/secondary master\n[    6.230767]  14c2c000.i3c12: INHOUSE control at offset 0xd00\n[    6.237082]  14c2c000.i3c12: PHY control at offset 0xe00\n[    6.243023]  14c2c000.i3c12: Using DMA\n[    6.247354] i3c 14c2c000.i3c12: Master Mode\n[    6.252037] i3c 14c2c000.i3c12: core rate \u003d 250000000 core period \u003d 4 ns\n[    6.259549] i3c 14c2c000.i3c12: 1 DMA rings available\n[    6.265221] mipi-i3c-hci 14c2c000.i3c12: assigned reserved memory node i3c12-reserved@431c3c000\n[    6.274950] i3c 14c2c000.i3c12: Ring 0 at offset 0x830\n[    6.281925]  14c2d000.i3c13: MIPI I3C HCI v1.1 r00\n[    6.287297]  14c2d000.i3c13: DAT: 127 8-bytes entries at offset 0x100\n[    6.294503]  14c2d000.i3c13: DCT: 1 16-bytes entries at offset 0x500\n[    6.301600]  14c2d000.i3c13: Ring Headers at offset 0x800\n[    6.307631]  14c2d000.i3c13: PIO section at offset 0xd0\n[    6.313467]  14c2d000.i3c13: Extended Caps at offset 0xf00\n[    6.319595]  14c2d000.i3c13: vendor MIPI ID: 0x3f6\n[    6.324947]  14c2d000.i3c13: vendor version ID: 0x2\n[    6.330395]  14c2d000.i3c13: vendor product ID: 0x6020003\n[    6.336425]  14c2d000.i3c13: operation mode: primary/secondary master\n[    6.343628]  14c2d000.i3c13: INHOUSE control at offset 0xd00\n[    6.349949]  14c2d000.i3c13: PHY control at offset 0xe00\n[    6.355886]  14c2d000.i3c13: Using DMA\n[    6.360201] i3c 14c2d000.i3c13: Master Mode\n[    6.364878] i3c 14c2d000.i3c13: core rate \u003d 250000000 core period \u003d 4 ns\n[    6.372385] i3c 14c2d000.i3c13: 1 DMA rings available\n[    6.378058] mipi-i3c-hci 14c2d000.i3c13: assigned reserved memory node i3c13-reserved@431c41000\n[    6.387768] i3c 14c2d000.i3c13: Ring 0 at offset 0x830\n[    6.394669]  14c2e000.i3c14: MIPI I3C HCI v1.1 r00\n[    6.400038]  14c2e000.i3c14: DAT: 127 8-bytes entries at offset 0x100\n[    6.407241]  14c2e000.i3c14: DCT: 1 16-bytes entries at offset 0x500\n[    6.414340]  14c2e000.i3c14: Ring Headers at offset 0x800\n[    6.420376]  14c2e000.i3c14: PIO section at offset 0xd0\n[    6.426212]  14c2e000.i3c14: Extended Caps at offset 0xf00\n[    6.432344]  14c2e000.i3c14: vendor MIPI ID: 0x3f6\n[    6.437694]  14c2e000.i3c14: vendor version ID: 0x2\n[    6.443147]  14c2e000.i3c14: vendor product ID: 0x6020003\n[    6.449181]  14c2e000.i3c14: operation mode: primary/secondary master\n[    6.456380]  14c2e000.i3c14: INHOUSE control at offset 0xd00\n[    6.462696]  14c2e000.i3c14: PHY control at offset 0xe00\n[    6.468633]  14c2e000.i3c14: Using DMA\n[    6.472976] i3c 14c2e000.i3c14: Master Mode\n[    6.477653] i3c 14c2e000.i3c14: core rate \u003d 250000000 core period \u003d 4 ns\n[    6.485165] i3c 14c2e000.i3c14: 1 DMA rings available\n[    6.490842] mipi-i3c-hci 14c2e000.i3c14: assigned reserved memory node i3c14-reserved@431c46000\n[    6.500566] i3c 14c2e000.i3c14: Ring 0 at offset 0x830\n[    6.507418]  14c2f000.i3c15: MIPI I3C HCI v1.1 r00\n[    6.512802]  14c2f000.i3c15: DAT: 127 8-bytes entries at offset 0x100\n[    6.520006]  14c2f000.i3c15: DCT: 1 16-bytes entries at offset 0x500\n[    6.527113]  14c2f000.i3c15: Ring Headers at offset 0x800\n[    6.533144]  14c2f000.i3c15: PIO section at offset 0xd0\n[    6.538985]  14c2f000.i3c15: Extended Caps at offset 0xf00\n[    6.545113]  14c2f000.i3c15: vendor MIPI ID: 0x3f6\n[    6.550472]  14c2f000.i3c15: vendor version ID: 0x2\n[    6.555925]  14c2f000.i3c15: vendor product ID: 0x6020003\n[    6.561948]  14c2f000.i3c15: operation mode: primary/secondary master\n[    6.569147]  14c2f000.i3c15: INHOUSE control at offset 0xd00\n[    6.575465]  14c2f000.i3c15: PHY control at offset 0xe00\n[    6.581402]  14c2f000.i3c15: Using DMA\n[    6.585717] i3c 14c2f000.i3c15: Master Mode\n[    6.590393] i3c 14c2f000.i3c15: core rate \u003d 250000000 core period \u003d 4 ns\n[    6.597905] i3c 14c2f000.i3c15: 1 DMA rings available\n[    6.603583] mipi-i3c-hci 14c2f000.i3c15: assigned reserved memory node i3c15-reserved@431c4b000\n[    6.613307] i3c 14c2f000.i3c15: Ring 0 at offset 0x830\n\nI3C Hub debugfs access:\nroot@:/sys/kernel/debug/i3c-hub-12-4cd34a94119/reg# echo 0 \u003e offset \u0026\u0026 cat access\n0x87\nroot@:/sys/kernel/debug/i3c-hub-12-4cd34a94119/reg# cd ..\nroot@:/sys/kernel/debug/i3c-hub-12-4cd34a94119# cd ..\nroot@:/sys/kernel/debug# cd i3c-hub-13-4cd86a14119/\nroot@:/sys/kernel/debug/i3c-hub-13-4cd86a14119# cd reg/\nroot@:/sys/kernel/debug/i3c-hub-13-4cd86a14119/reg# echo 0 \u003e offset \u0026\u0026 cat access\n0x87\nroot@:/sys/kernel/debug/i3c-hub-13-4cd86a14119/reg# cd ../../\nroot@:/sys/kernel/debug# cd i3c-hub-14-4cd8ea7411d/reg/\nroot@:/sys/kernel/debug/i3c-hub-14-4cd8ea7411d/reg# echo 0 \u003e offset \u0026\u0026 cat access\n0x87\nroot@:/sys/kernel/debug/i3c-hub-14-4cd8ea7411d/reg# cd ../../\nroot@:/sys/kernel/debug# cd i3c-hub-15-4cd2ab34115/reg/\nroot@:/sys/kernel/debug/i3c-hub-15-4cd2ab34115/reg# echo 0 \u003e offset \u0026\u0026 cat access\n0x87\n```\n\nGoogle-Bug-Id: 542414147\nChange-Id: I288fdf8482fbabbc4fb0ada526c8982175076d32\nSigned-off-by: Jake Chiang \u003chung-tse.chiang@fii-na.corp-partner.google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "15e3ed4c88b72f3042f1a5a4ec2214bef1d20a59",
      "old_mode": 57344,
      "old_path": "linux/6.18-ast27xx",
      "new_id": "dd52df9f7a7b66673b99e3840d2d02b6026ab851",
      "new_mode": 57344,
      "new_path": "linux/6.18-ast27xx"
    }
  ]
}