)]}'
{
  "commit": "1cbdfcfd08c4f47b8019c4f34a2c87fe6c444a31",
  "tree": "48a90d69dc2a55532ce756903565aeab5241c994",
  "parents": [
    "0b28f9ee4b993621258615b591f0175c30340b06"
  ],
  "author": {
    "name": "Théo Lebrun",
    "email": "theo.lebrun@bootlin.com",
    "time": "Wed Nov 06 17:03:59 2024 +0100"
  },
  "committer": {
    "name": "Stephen Boyd",
    "email": "sboyd@kernel.org",
    "time": "Thu Nov 14 14:52:27 2024 -0800"
  },
  "message": "clk: eyeq: add EyeQ6H west fixed factor clocks\n\nPrevious setup was:\n - pll-west clock registered from driver at of_clk_init();\n - Both OCC and UART clocks registered from DT using fixed-factor-clock\n   compatible.\n\nNow that drivers/clk/clk-eyeq.c supports registering fixed factors, use\nthat capability to register west-per-occ and west-per-uart (giving them\nproper names at the same time).\n\nAlso switch from hard-coded index 0 for pll-west to using the\nEQ6HC_WEST_PLL_PER constant by exposed dt-bindings headers.\n\nAll get exposed at of_clk_init() because they get used by the AMBA PL011\nserial ports. Those are instantiated before platform bus infrastructure.\n\nSigned-off-by: Théo Lebrun \u003ctheo.lebrun@bootlin.com\u003e\nLink: https://lore.kernel.org/r/20241106-mbly-clk-v2-8-84cfefb3f485@bootlin.com\nSigned-off-by: Stephen Boyd \u003csboyd@kernel.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a042e9735b68f85c1ad79ec963b0268410b87ad4",
      "old_mode": 33188,
      "old_path": "drivers/clk/clk-eyeq.c",
      "new_id": "640c25788487f8cf6fb4431ed6fb612cf099f114",
      "new_mode": 33188,
      "new_path": "drivers/clk/clk-eyeq.c"
    }
  ]
}