tree 9059d5635436457b2f978db26c104c606a5814cc
parent f8470006c4d6bd54dbf9a3479f85e13387bff56d
parent 98d1fb94ce75f39febd456d6d3cbbe58b6678795
author Miquel Raynal <miquel.raynal@bootlin.com> 1732014924 +0100
committer Miquel Raynal <miquel.raynal@bootlin.com> 1732014924 +0100
mergetag object 98d1fb94ce75f39febd456d6d3cbbe58b6678795
 type commit
 tag spi-nor/for-6.13
 tagger Tudor Ambarus <tudor.ambarus@linaro.org> 1731401251 +0200
 
 SPI NOR introduces byte swap support for 8D-8D-8D mode and a user for
 it: macronix. SPI NOR flashes may swap the bytes on a 16-bit boundary
 when configured in Octal DTR mode. For such cases the byte order is
 propagated through SPI MEM to the SPI controllers so that the controllers
 swap the bytes back at runtime. This avoids breaking the boot sequence
 because of the endianness problems that appear when the bootloaders use
 1-1-1 and the kernel uses 8D-8D-8D with byte swap support. Along with the
 SPI MEM byte swap support we queue a patch for the SPI MXIC controller
 that swaps the bytes back at runtime.
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Merge tag 'spi-nor/for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next

SPI NOR introduces byte swap support for 8D-8D-8D mode and a user for
it: macronix. SPI NOR flashes may swap the bytes on a 16-bit boundary
when configured in Octal DTR mode. For such cases the byte order is
propagated through SPI MEM to the SPI controllers so that the controllers
swap the bytes back at runtime. This avoids breaking the boot sequence
because of the endianness problems that appear when the bootloaders use
1-1-1 and the kernel uses 8D-8D-8D with byte swap support. Along with the
SPI MEM byte swap support we queue a patch for the SPI MXIC controller
that swaps the bytes back at runtime.

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# gpg: Signature made Tue 12 Nov 2024 10:12:26 AM CET
# gpg:                using RSA key 1D422ACACF0EC86D5E1DFEDF4B554F47A58D14E9
# gpg: Good signature from "Tudor Ambarus (4096-bit rsa key) <tudor.ambarus@microchip.com>" [full]
# gpg:                 aka "Tudor Ambarus <tudor.ambarus@gmail.com>" [full]
# gpg: tudor.ambarus@microchip.com: Verified 15 signatures in the past 5 years.
#      Encrypted 0 messages.
# gpg: tudor.ambarus@gmail.com: Verified 15 signatures in the past 5 years.
#      Encrypted 0 messages.