)]}'
{
  "commit": "3c60184e39b57e5efe664fe8540cdbc1bc7ea899",
  "tree": "9f1e83fec35e132bd02065e5b1edaf4085b7fa93",
  "parents": [
    "5ac5ec84734fd338867055d4d7b650f18a023cb0"
  ],
  "author": {
    "name": "Peng Yang",
    "email": "pyangyyd@gmail.com",
    "time": "Mon Jun 08 17:58:49 2026 +0800"
  },
  "committer": {
    "name": "Mark Brown",
    "email": "broonie@kernel.org",
    "time": "Wed Jun 10 00:07:39 2026 +0100"
  },
  "message": "spi: dw: fix race between IRQ handler and error handler on SMP\n\nOn SMP systems, dw_spi_handle_err() can be called from the SPI core\nkthread while the IRQ handler is still accessing the FIFO on another\nCPU. Resetting the chip via dw_spi_reset_chip() during an active FIFO\nread/write causes a bus error.\n\nFix this by calling disable_irq() before the chip reset, which masks\nthe IRQ and waits for any in-flight handler to complete via\nsynchronize_irq(). This ensures no handler is accessing the FIFO when\nthe reset occurs.\n\nSigned-off-by: Peng Yang \u003cpyangyyd@amazon.com\u003e\nSuggested-by: Jonathan Chocron \u003cjonnyc@amazon.com\u003e\nLink: https://patch.msgid.link/20260608095849.3446-1-pyangyyd@amazon.com\nSigned-off-by: Mark Brown \u003cbroonie@kernel.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b47637888c5c6f650e2f840748cf4e10ad96e377",
      "old_mode": 33188,
      "old_path": "drivers/spi/spi-dw-core.c",
      "new_id": "4672bc2a873a714b38d8ee5597f17c70b9269b61",
      "new_mode": 33188,
      "new_path": "drivers/spi/spi-dw-core.c"
    }
  ]
}