// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2025 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
 * Copyright (C) 2025 Engicam srl
 */

/dts-v1/;

 #include "imx6ull.dtsi"

/ {
	compatible = "engicam,microgea-imx6ull", "fsl,imx6ull";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_phy_reset>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	local-mac-address = [00 00 00 00 00 00];
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
			reset-assert-us = <4000>;
			reset-deassert-us = <4000>;
		};
	};
};

/* NAND */
&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-ecc-mode = "hw";
	nand-ecc-strength = <0>;
	nand-ecc-step-size = <0>;
	nand-on-flash-bbt;
	status = "okay";
};

&iomuxc {
	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b009
			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
		>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0xb0b1
			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0xb0b1
			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0xb0b1
			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0xb000
			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0xb0b1
			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0xb0b1
			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0xb0b1
			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0xb0b1
			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0xb0b1
			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0xb0b1
			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0xb0b1
			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0xb0b1
			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0xb0b1
			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0xb0b1
			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0xb0b1
		>;
	};
};

&iomuxc_snvs {
	pinctrl_phy_reset: phy-resetgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x1b0b0
		>;
	};
};