// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2022 Microchip Technology Inc */

/ {
	fabric_clk3: fabric-clk3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <62500000>;
	};

	fabric_clk1: fabric-clk1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
	};

	pcie: pcie@2000000000 {
		compatible = "microchip,pcie-host-1.0";
		#address-cells = <0x3>;
		#interrupt-cells = <0x1>;
		#size-cells = <0x2>;
		device_type = "pci";
		reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
		      <0x0 0x4300a000 0x0 0x2000>;
		reg-names = "cfg", "bridge", "ctrl";
		bus-range = <0x0 0x7f>;
		interrupt-parent = <&plic>;
		interrupts = <119>;
		interrupt-map = <0 0 0 1 &pcie_intc 0>,
				<0 0 0 2 &pcie_intc 1>,
				<0 0 0 3 &pcie_intc 2>,
				<0 0 0 4 &pcie_intc 3>;
		interrupt-map-mask = <0 0 0 7>;
		clocks = <&fabric_clk1>, <&fabric_clk3>;
		clock-names = "fic0", "fic3";
		ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
		msi-parent = <&pcie>;
		msi-controller;
		status = "disabled";
		pcie_intc: interrupt-controller {
			#address-cells = <0>;
			#interrupt-cells = <1>;
			interrupt-controller;
		};
	};
};