# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8qxp Display Controller interrupt controller

description: |
  The Display Controller has a built-in interrupt controller with the following
  features for all relevant HW events:

  * Enable bit (mask)
  * Status bit (set by an HW event)
  * Preset bit (can be used by SW to set status)
  * Clear bit (used by SW to reset the status)

  Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
  Alternatively the un-masked trigger signals for all HW events are provided,
  allowing it to use a global interrupt controller instead.

  Each interrupt can be protected against SW running in user mode. In that case,
  only privileged AHB access can control the interrupt status.

maintainers:
  - Liu Ying <victor.liu@nxp.com>

properties:
  compatible:
    const: fsl,imx8qxp-dc-intc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupt-controller: true

  "#interrupt-cells":
    const: 1

  interrupts:
    items:
      - description: store9 shadow load interrupt(blit engine)
      - description: store9 frame complete interrupt(blit engine)
      - description: store9 sequence complete interrupt(blit engine)
      - description:
          extdst0 shadow load interrupt
          (display controller, content stream 0)
      - description:
          extdst0 frame complete interrupt
          (display controller, content stream 0)
      - description:
          extdst0 sequence complete interrupt
          (display controller, content stream 0)
      - description:
          extdst4 shadow load interrupt
          (display controller, safety stream 0)
      - description:
          extdst4 frame complete interrupt
          (display controller, safety stream 0)
      - description:
          extdst4 sequence complete interrupt
          (display controller, safety stream 0)
      - description:
          extdst1 shadow load interrupt
          (display controller, content stream 1)
      - description:
          extdst1 frame complete interrupt
          (display controller, content stream 1)
      - description:
          extdst1 sequence complete interrupt
          (display controller, content stream 1)
      - description:
          extdst5 shadow load interrupt
          (display controller, safety stream 1)
      - description:
          extdst5 frame complete interrupt
          (display controller, safety stream 1)
      - description:
          extdst5 sequence complete interrupt
          (display controller, safety stream 1)
      - description:
          disengcfg0 shadow load interrupt
          (display controller, display stream 0)
      - description:
          disengcfg0 frame complete interrupt
          (display controller, display stream 0)
      - description:
          disengcfg0 sequence complete interrupt
          (display controller, display stream 0)
      - description:
          framegen0 programmable interrupt0
          (display controller, display stream 0)
      - description:
          framegen0 programmable interrupt1
          (display controller, display stream 0)
      - description:
          framegen0 programmable interrupt2
          (display controller, display stream 0)
      - description:
          framegen0 programmable interrupt3
          (display controller, display stream 0)
      - description:
          signature0 shadow load interrupt
          (display controller, display stream 0)
      - description:
          signature0 measurement valid interrupt
          (display controller, display stream 0)
      - description:
          signature0 error condition interrupt
          (display controller, display stream 0)
      - description:
          disengcfg1 shadow load interrupt
          (display controller, display stream 1)
      - description:
          disengcfg1 frame complete interrupt
          (display controller, display stream 1)
      - description:
          disengcfg1 sequence complete interrupt
          (display controller, display stream 1)
      - description:
          framegen1 programmable interrupt0
          (display controller, display stream 1)
      - description:
          framegen1 programmable interrupt1
          (display controller, display stream 1)
      - description:
          framegen1 programmable interrupt2
          (display controller, display stream 1)
      - description:
          framegen1 programmable interrupt3
          (display controller, display stream 1)
      - description:
          signature1 shadow load interrupt
          (display controller, display stream 1)
      - description:
          signature1 measurement valid interrupt
          (display controller, display stream 1)
      - description:
          signature1 error condition interrupt
          (display controller, display stream 1)
      - description: reserved
      - description:
          command sequencer error condition interrupt(command sequencer)
      - description:
          common control software interrupt0(common control)
      - description:
          common control software interrupt1(common control)
      - description:
          common control software interrupt2(common control)
      - description:
          common control software interrupt3(common control)
      - description:
          framegen0 synchronization status activated interrupt
          (display controller, safety stream 0)
      - description:
          framegen0 synchronization status deactivated interrupt
          (display controller, safety stream 0)
      - description:
          framegen0 synchronization status activated interrupt
          (display controller, content stream 0)
      - description:
          framegen0 synchronization status deactivated interrupt
          (display controller, content stream 0)
      - description:
          framegen1 synchronization status activated interrupt
          (display controller, safety stream 1)
      - description:
          framegen1 synchronization status deactivated interrupt
          (display controller, safety stream 1)
      - description:
          framegen1 synchronization status activated interrupt
          (display controller, content stream 1)
      - description:
          framegen1 synchronization status deactivated interrupt
          (display controller, content stream 1)
    minItems: 49

  interrupt-names:
    items:
      - const: store9_shdload
      - const: store9_framecomplete
      - const: store9_seqcomplete
      - const: extdst0_shdload
      - const: extdst0_framecomplete
      - const: extdst0_seqcomplete
      - const: extdst4_shdload
      - const: extdst4_framecomplete
      - const: extdst4_seqcomplete
      - const: extdst1_shdload
      - const: extdst1_framecomplete
      - const: extdst1_seqcomplete
      - const: extdst5_shdload
      - const: extdst5_framecomplete
      - const: extdst5_seqcomplete
      - const: disengcfg_shdload0
      - const: disengcfg_framecomplete0
      - const: disengcfg_seqcomplete0
      - const: framegen0_int0
      - const: framegen0_int1
      - const: framegen0_int2
      - const: framegen0_int3
      - const: sig0_shdload
      - const: sig0_valid
      - const: sig0_error
      - const: disengcfg_shdload1
      - const: disengcfg_framecomplete1
      - const: disengcfg_seqcomplete1
      - const: framegen1_int0
      - const: framegen1_int1
      - const: framegen1_int2
      - const: framegen1_int3
      - const: sig1_shdload
      - const: sig1_valid
      - const: sig1_error
      - const: reserved
      - const: cmdseq_error
      - const: comctrl_sw0
      - const: comctrl_sw1
      - const: comctrl_sw2
      - const: comctrl_sw3
      - const: framegen0_primsync_on
      - const: framegen0_primsync_off
      - const: framegen0_secsync_on
      - const: framegen0_secsync_off
      - const: framegen1_primsync_on
      - const: framegen1_primsync_off
      - const: framegen1_secsync_on
      - const: framegen1_secsync_off
    minItems: 49

required:
  - compatible
  - reg
  - clocks
  - interrupt-controller
  - "#interrupt-cells"
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8-lpcg.h>

    interrupt-controller@56180040 {
        compatible = "fsl,imx8qxp-dc-intc";
        reg = <0x56180040 0x60>;
        clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
        interrupt-controller;
        interrupt-parent = <&dc0_irqsteer>;
        #interrupt-cells = <1>;
        interrupts = <448>, <449>, <450>,  <64>,
                      <65>,  <66>,  <67>,  <68>,
                      <69>,  <70>, <193>, <194>,
                     <195>, <196>, <197>,  <72>,
                      <73>,  <74>,  <75>,  <76>,
                      <77>,  <78>,  <79>,  <80>,
                      <81>, <199>, <200>, <201>,
                     <202>, <203>, <204>, <205>,
                     <206>, <207>, <208>,   <5>,
                       <0>,   <1>,   <2>,   <3>,
                       <4>,  <82>,  <83>,  <84>,
                      <85>, <209>, <210>, <211>,
                     <212>;
        interrupt-names = "store9_shdload",
                          "store9_framecomplete",
                          "store9_seqcomplete",
                          "extdst0_shdload",
                          "extdst0_framecomplete",
                          "extdst0_seqcomplete",
                          "extdst4_shdload",
                          "extdst4_framecomplete",
                          "extdst4_seqcomplete",
                          "extdst1_shdload",
                          "extdst1_framecomplete",
                          "extdst1_seqcomplete",
                          "extdst5_shdload",
                          "extdst5_framecomplete",
                          "extdst5_seqcomplete",
                          "disengcfg_shdload0",
                          "disengcfg_framecomplete0",
                          "disengcfg_seqcomplete0",
                          "framegen0_int0",
                          "framegen0_int1",
                          "framegen0_int2",
                          "framegen0_int3",
                          "sig0_shdload",
                          "sig0_valid",
                          "sig0_error",
                          "disengcfg_shdload1",
                          "disengcfg_framecomplete1",
                          "disengcfg_seqcomplete1",
                          "framegen1_int0",
                          "framegen1_int1",
                          "framegen1_int2",
                          "framegen1_int3",
                          "sig1_shdload",
                          "sig1_valid",
                          "sig1_error",
                          "reserved",
                          "cmdseq_error",
                          "comctrl_sw0",
                          "comctrl_sw1",
                          "comctrl_sw2",
                          "comctrl_sw3",
                          "framegen0_primsync_on",
                          "framegen0_primsync_off",
                          "framegen0_secsync_on",
                          "framegen0_secsync_off",
                          "framegen1_primsync_on",
                          "framegen1_primsync_off",
                          "framegen1_secsync_on",
                          "framegen1_secsync_off";
    };