# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/nxp,lpc1850-rgu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP LPC1850  Reset Generation Unit (RGU)

maintainers:
  - Frank Li <Frank.Li@nxp.com>

properties:
  compatible:
    const: nxp,lpc1850-rgu

  reg:
    maxItems: 1

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: delay
      - const: reg

  '#reset-cells':
    const: 1
    description: |
      See table below for valid peripheral reset numbers. Numbers not
      in the table below are either reserved or not applicable for
      normal operation.

      Reset	Peripheral
        9	System control unit (SCU)
       12	ARM Cortex-M0 subsystem core (LPC43xx only)
       13	CPU core
       16	LCD controller
       17	USB0
       18	USB1
       19	DMA
       20	SDIO
       21	External memory controller (EMC)
       22	Ethernet
       25	Flash bank A
       27	EEPROM
       28	GPIO
       29	Flash bank B
       32	Timer0
       33	Timer1
       34	Timer2
       35	Timer3
       36	Repetitive Interrupt timer (RIT)
       37	State Configurable Timer (SCT)
       38	Motor control PWM (MCPWM)
       39	QEI
       40	ADC0
       41	ADC1
       42	DAC
       44	USART0
       45	UART1
       46	USART2
       47	USART3
       48	I2C0
       49	I2C1
       50	SSP0
       51	SSP1
       52	I2S0 and I2S1
       53	Serial Flash Interface (SPIFI)
       54	C_CAN1
       55	C_CAN0
       56	ARM Cortex-M0 application core (LPC4370 only)
       57	SGPIO (LPC43xx only)
       58	SPI (LPC43xx only)
       60	ADCHS (12-bit ADC) (LPC4370 only)

      Refer to NXP LPC18xx or LPC43xx user manual for more details about
      the reset signals and the connected block/peripheral.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#reset-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/lpc18xx-ccu.h>
    #include <dt-bindings/clock/lpc18xx-cgu.h>

    reset-controller@40053000 {
        compatible = "nxp,lpc1850-rgu";
        reg = <0x40053000 0x1000>;
        clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
        clock-names = "delay", "reg";
        #reset-cells = <1>;
    };