# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/st,stm32-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 SPI Controller

description: |
  The STM32 SPI controller is used to communicate with external devices using
  the Serial Peripheral Interface. It supports full-duplex, half-duplex and
  simplex synchronous serial communication with external devices. It supports
  from 4 to 32-bit data size.

maintainers:
  - Erwan Leray <erwan.leray@foss.st.com>
  - Fabrice Gasnier <fabrice.gasnier@foss.st.com>

allOf:
  - $ref: spi-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: st,stm32f4-spi

    then:
      properties:
        st,spi-midi-ns: false
        sram: false
        dmas:
          maxItems: 2
        dma-names:
          items:
            - const: rx
            - const: tx

  - if:
      properties:
        compatible:
          contains:
            const: st,stm32mp25-spi

    then:
      properties:
        sram: false
        dmas:
          maxItems: 2
        dma-names:
          items:
            - const: rx
            - const: tx

properties:
  compatible:
    enum:
      - st,stm32f4-spi
      - st,stm32f7-spi
      - st,stm32h7-spi
      - st,stm32mp25-spi

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  resets:
    maxItems: 1

  dmas:
    description: |
      DMA specifiers for tx and rx channels. DMA fifo mode must be used. See
      the STM32 DMA bindings Documentation/devicetree/bindings/dma/stm32/st,*dma.yaml
    minItems: 2
    items:
      - description: rx DMA channel
      - description: tx DMA channel
      - description: rxm2m MDMA channel

  dma-names:
    minItems: 2
    items:
      - const: rx
      - const: tx
      - const: rxm2m

  sram:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      Phandles to a reserved SRAM region which is used as temporary
      storage memory between DMA and MDMA engines.
      The region should be defined as child node of the AHB SRAM node
      as per the generic bindings in Documentation/devicetree/bindings/sram/sram.yaml

  access-controllers:
    minItems: 1
    maxItems: 2

required:
  - compatible
  - reg
  - clocks
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    spi@4000b000 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "st,stm32h7-spi";
        reg = <0x4000b000 0x400>;
        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&rcc SPI2_K>;
        resets = <&rcc SPI2_R>;
        dmas = <&dmamux1 0 39 0x400 0x05>,
               <&dmamux1 1 40 0x400 0x05>;
        dma-names = "rx", "tx";
        cs-gpios = <&gpioa 11 0>;
    };

...