# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm7150-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM7150 Display MDSS

maintainers:
  - Danila Tikhonov <danila@jiaxyga.com>

description:
  SM7150 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
  DPU display controller, DSI and DP interfaces etc.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    const: qcom,sm7150-mdss

  clocks:
    items:
      - description: Display ahb clock from gcc
      - description: Display hf axi clock
      - description: Display sf axi clock
      - description: Display core clock

  clock-names:
    items:
      - const: iface
      - const: bus
      - const: nrt_bus
      - const: core

  iommus:
    maxItems: 1

  interconnects:
    items:
      - description: Interconnect path from mdp0 port to the data bus
      - description: Interconnect path from mdp1 port to the data bus
      - description: Interconnect path from CPU to the reg bus

  interconnect-names:
    items:
      - const: mdp0-mem
      - const: mdp1-mem
      - const: cpu-cfg

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true
    properties:
      compatible:
        const: qcom,sm7150-dpu

  "^displayport-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true
    properties:
      compatible:
        contains:
          const: qcom,sm7150-dp

  "^dsi@[0-9a-f]+$":
    type: object
    additionalProperties: true
    properties:
      compatible:
        items:
          - const: qcom,sm7150-dsi-ctrl
          - const: qcom,mdss-dsi-ctrl

  "^phy@[0-9a-f]+$":
    type: object
    additionalProperties: true
    properties:
      compatible:
        const: qcom,dsi-phy-10nm

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/interconnect/qcom,icc.h>
    #include <dt-bindings/interconnect/qcom,sm7150-rpmh.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>

    display-subsystem@ae00000 {
        compatible = "qcom,sm7150-mdss";
        reg = <0x0ae00000 0x1000>;
        reg-names = "mdss";

        power-domains = <&dispcc_mdss_gdsc>;

        clocks = <&dispcc_mdss_ahb_clk>,
                 <&gcc_disp_hf_axi_clk>,
                 <&gcc_disp_sf_axi_clk>,
                 <&dispcc_mdss_mdp_clk>;
        clock-names = "iface",
                      "bus",
                      "nrt_bus",
                      "core";

        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;

        interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS
                         &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
                        <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS
                         &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
                        <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
                         &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
        interconnect-names = "mdp0-mem",
                             "mdp1-mem",
                             "cpu-cfg";

        iommus = <&apps_smmu 0x800 0x440>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        display-controller@ae01000 {
            compatible = "qcom,sm7150-dpu";
            reg = <0x0ae01000 0x8f000>,
                  <0x0aeb0000 0x2008>;
            reg-names = "mdp", "vbif";

            clocks = <&gcc_disp_hf_axi_clk>,
                     <&dispcc_mdss_ahb_clk>,
                     <&dispcc_mdss_rot_clk>,
                     <&dispcc_mdss_mdp_lut_clk>,
                     <&dispcc_mdss_mdp_clk>,
                     <&dispcc_mdss_vsync_clk>;
            clock-names = "bus",
                          "iface",
                          "rot",
                          "lut",
                          "core",
                          "vsync";

            assigned-clocks = <&dispcc_mdss_vsync_clk>;
            assigned-clock-rates = <19200000>;

            operating-points-v2 = <&mdp_opp_table>;
            power-domains = <&rpmhpd RPMHPD_CX>;

            interrupt-parent = <&mdss>;
            interrupts = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&mdss_dsi0_in>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dpu_intf2_out: endpoint {
                        remote-endpoint = <&mdss_dsi1_in>;
                    };
                };

                port@2 {
                    reg = <2>;
                    dpu_intf0_out: endpoint {
                        remote-endpoint = <&dp_in>;
                    };
                };
            };

            mdp_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-19200000 {
                    opp-hz = /bits/ 64 <19200000>;
                    required-opps = <&rpmhpd_opp_min_svs>;
                };

                opp-200000000 {
                    opp-hz = /bits/ 64 <200000000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-300000000 {
                    opp-hz = /bits/ 64 <300000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-344000000 {
                    opp-hz = /bits/ 64 <344000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };

                opp-430000000 {
                    opp-hz = /bits/ 64 <430000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };
            };
        };

        dsi@ae94000 {
            compatible = "qcom,sm7150-dsi-ctrl",
                         "qcom,mdss-dsi-ctrl";
            reg = <0x0ae94000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <4>;

            clocks = <&dispcc_mdss_byte0_clk>,
                     <&dispcc_mdss_byte0_intf_clk>,
                     <&dispcc_mdss_pclk0_clk>,
                     <&dispcc_mdss_esc0_clk>,
                     <&dispcc_mdss_ahb_clk>,
                     <&gcc_disp_hf_axi_clk>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";

            assigned-clocks = <&dispcc_mdss_byte0_clk_src>,
                              <&dispcc_mdss_pclk0_clk_src>;
            assigned-clock-parents = <&mdss_dsi0_phy 0>,
                                     <&mdss_dsi0_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmhpd RPMHPD_CX>;

            phys = <&mdss_dsi0_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    mdss_dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    mdss_dsi0_out: endpoint {
                    };
                };
            };

            dsi_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-180000000 {
                    opp-hz = /bits/ 64 <180000000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-275000000 {
                    opp-hz = /bits/ 64 <275000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-358000000 {
                    opp-hz = /bits/ 64 <358000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };
            };
        };

        mdss_dsi0_phy: phy@ae94400 {
            compatible = "qcom,dsi-phy-10nm";
            reg = <0x0ae94400 0x200>,
                  <0x0ae94600 0x280>,
                  <0x0ae94a00 0x1e0>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc_mdss_ahb_clk>,
                     <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "iface", "ref";
            vdds-supply = <&vdda_mipi_dsi0_pll>;
        };

        dsi@ae96000 {
            compatible = "qcom,sm7150-dsi-ctrl",
                         "qcom,mdss-dsi-ctrl";
            reg = <0x0ae96000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <5>;

            clocks = <&dispcc_mdss_byte1_clk>,
                     <&dispcc_mdss_byte1_intf_clk>,
                     <&dispcc_mdss_pclk1_clk>,
                     <&dispcc_mdss_esc1_clk>,
                     <&dispcc_mdss_ahb_clk>,
                     <&gcc_disp_hf_axi_clk>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";

            assigned-clocks = <&dispcc_mdss_byte1_clk_src>,
                              <&dispcc_mdss_pclk1_clk_src>;
            assigned-clock-parents = <&mdss_dsi1_phy 0>,
                                     <&mdss_dsi1_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmhpd RPMHPD_CX>;

            phys = <&mdss_dsi1_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    mdss_dsi1_in: endpoint {
                        remote-endpoint = <&dpu_intf2_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    mdss_dsi1_out: endpoint {
                    };
                };
            };
        };

        mdss_dsi1_phy: phy@ae96400 {
            compatible = "qcom,dsi-phy-10nm";
            reg = <0x0ae96400 0x200>,
                  <0x0ae96600 0x280>,
                  <0x0ae96a00 0x1e0>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc_mdss_ahb_clk>,
                     <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "iface", "ref";
            vdds-supply = <&vdda_mipi_dsi1_pll>;
        };

        displayport-controller@ae90000 {
            compatible = "qcom,sm7150-dp",
                         "qcom,sm8350-dp";
            reg = <0xae90000 0x200>,
                  <0xae90200 0x200>,
                  <0xae90400 0xc00>,
                  <0xae91000 0x400>,
                  <0xae91400 0x400>;

            interrupt-parent = <&mdss>;
            interrupts = <12>;

            clocks = <&dispcc_mdss_ahb_clk>,
                     <&dispcc_mdss_dp_aux_clk>,
                     <&dispcc_mdss_dp_link_clk>,
                     <&dispcc_mdss_dp_link_intf_clk>,
                     <&dispcc_mdss_dp_pixel_clk>,
                     <&dispcc_mdss_dp_pixel1_clk>;
            clock-names = "core_iface",
                          "core_aux",
                          "ctrl_link",
                          "ctrl_link_iface",
                          "stream_pixel",
                          "stream_1_pixel";

            assigned-clocks = <&dispcc_mdss_dp_link_clk_src>,
                              <&dispcc_mdss_dp_pixel_clk_src>,
                              <&dispcc_mdss_dp_pixel1_clk_src>;
            assigned-clock-parents = <&dp_phy 0>,
                                     <&dp_phy 1>,
                                     <&dp_phy 1>;

            operating-points-v2 = <&dp_opp_table>;
            power-domains = <&rpmhpd RPMHPD_CX>;

            phys = <&dp_phy>;
            phy-names = "dp";

            #sound-dai-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dp_in: endpoint {
                        remote-endpoint = <&dpu_intf0_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dp_out: endpoint {
                    };
                };
            };

            dp_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-160000000 {
                    opp-hz = /bits/ 64 <160000000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-270000000 {
                    opp-hz = /bits/ 64 <270000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-540000000 {
                    opp-hz = /bits/ 64 <540000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };

                opp-810000000 {
                    opp-hz = /bits/ 64 <810000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };
            };
        };
    };
...