Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Nested Vector Interrupt Controller (NVIC)

maintainers:
  - Rob Herring <robh@kernel.org>

description:
  The NVIC provides an interrupt controller that is tightly coupled to Cortex-M
  based processor cores.  The NVIC implemented on different SoCs vary in the
  number of interrupts and priority bits per interrupt.

properties:
  compatible:
    enum:
      - arm,v6m-nvic
      - arm,v7m-nvic
      - arm,v8m-nvic

  reg:
    maxItems: 1

  '#address-cells':
    const: 0

  interrupt-controller: true

  '#interrupt-cells':
    const: 2
    description: |
      Number of cells to encode an interrupt source:
      first = interrupt number, second = priority.

  arm,num-irq-priority-bits:
    description: Number of priority bits implemented by the SoC
    minimum: 1
    maximum: 8

required:
  - compatible
  - reg
  - interrupt-controller
  - '#interrupt-cells'
  - arm,num-irq-priority-bits

additionalProperties: false

examples:
  - |
    interrupt-controller@e000e100 {
        compatible = "arm,v7m-nvic";
        #interrupt-cells = <2>;
        #address-cells = <0>;
        interrupt-controller;
        reg = <0xe000e100 0xc00>;
        arm,num-irq-priority-bits = <4>;
    };