# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence NAND controller

maintainers:
  - Niravkumar L Rabara <niravkumar.l.rabara@intel.com>

allOf:
  - $ref: nand-controller.yaml

properties:
  compatible:
    items:
      - const: cdns,hp-nfc

  reg:
    items:
      - description: Controller register set
      - description: Slave DMA data port register set

  reg-names:
    items:
      - const: reg
      - const: sdma

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: nf_clk

  dmas:
    maxItems: 1

  dma-coherent: true

  iommus:
    maxItems: 1

  cdns,board-delay-ps:
    description: |
      Estimated Board delay. The value includes the total round trip
      delay for the signals and is used for deciding on values associated
      with data read capture. The example formula for SDR mode is the
      following.
      board delay = RE#PAD delay + PCB trace to device + PCB trace from device
      + DQ PAD delay

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    nand-controller@10b80000 {
        compatible = "cdns,hp-nfc";
        reg = <0x10b80000 0x10000>,
              <0x10840000 0x10000>;
        reg-names = "reg", "sdma";
        #address-cells = <1>;
        #size-cells = <0>;
        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk>;
        clock-names = "nf_clk";
        cdns,board-delay-ps = <4830>;

        nand@0 {
            reg = <0>;
        };
    };