# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx93-media-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX93 Media blk-ctrl

maintainers:
  - Peng Fan <peng.fan@nxp.com>

description:
  The i.MX93 MEDIAMIX domain contains control and status registers known
  as MEDIAMIX Block Control (MEDIAMIX BLK_CTRL). These registers include
  clocking, reset, and miscellaneous top-level controls for peripherals
  within the MEDIAMIX domain

properties:
  compatible:
    items:
      - enum:
          - fsl,imx91-media-blk-ctrl
          - fsl,imx93-media-blk-ctrl
      - const: syscon

  reg:
    maxItems: 1

  '#power-domain-cells':
    const: 1

  power-domains:
    maxItems: 1

  clocks:
    minItems: 8
    maxItems: 10

  clock-names:
    minItems: 8
    maxItems: 10

  dpi-bridge:
    type: object
    additionalProperties: false

    properties:
      compatible:
        enum:
          - nxp,imx91-pdfc
          - nxp,imx93-pdfc

      ports:
        $ref: /schemas/graph.yaml#/properties/ports

        properties:
          port@0:
            $ref: /schemas/graph.yaml#/properties/port
            description: Input port node to receive pixel data.

          port@1:
            $ref: /schemas/graph.yaml#/$defs/port-base
            unevaluatedProperties: false
            description: Output port node to downstream pixel data receivers.

            properties:
              endpoint:
                $ref: /schemas/media/video-interfaces.yaml#
                unevaluatedProperties: false

                properties:
                  bus-width:
                    enum: [ 16, 18, 24 ]
                    description:
                      Specify the physical parallel bus width.

                      This property is optional if the display bus-width
                      matches the SoC bus-width, e.g. a 18-bit RGB666 (display)
                      is connected and all 18-bit data lines are muxed to the
                      parallel-output pads.

                      This property must be set to 18 to cut only the LSBs
                      instead of the MSBs in case a 24-bit RGB888 display is
                      connected and only the lower 18-bit data lanes are muxed
                      to the parallel-output pads.

        required:
          - port@0
          - port@1

    required:
      - compatible
      - ports

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx91-media-blk-ctrl
    then:
      properties:
        clocks:
          maxItems: 8
        clock-names:
          items:
            - const: apb
            - const: axi
            - const: nic
            - const: disp
            - const: cam
            - const: lcdif
            - const: isi
            - const: csi
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx93-media-blk-ctrl
    then:
      properties:
        clocks:
          minItems: 10
        clock-names:
          items:
            - const: apb
            - const: axi
            - const: nic
            - const: disp
            - const: cam
            - const: pxp
            - const: lcdif
            - const: isi
            - const: csi
            - const: dsi
required:
  - compatible
  - reg
  - power-domains
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx93-clock.h>
    #include <dt-bindings/power/fsl,imx93-power.h>

    system-controller@4ac10000 {
      compatible = "fsl,imx93-media-blk-ctrl", "syscon";
      reg = <0x4ac10000 0x10000>;
      power-domains = <&mediamix>;
      clocks = <&clk IMX93_CLK_MEDIA_APB>,
               <&clk IMX93_CLK_MEDIA_AXI>,
               <&clk IMX93_CLK_NIC_MEDIA_GATE>,
               <&clk IMX93_CLK_MEDIA_DISP_PIX>,
               <&clk IMX93_CLK_CAM_PIX>,
               <&clk IMX93_CLK_PXP_GATE>,
               <&clk IMX93_CLK_LCDIF_GATE>,
               <&clk IMX93_CLK_ISI_GATE>,
               <&clk IMX93_CLK_MIPI_CSI_GATE>,
               <&clk IMX93_CLK_MIPI_DSI_GATE>;
               clock-names = "apb", "axi", "nic", "disp", "cam",
                             "pxp", "lcdif", "isi", "csi", "dsi";
      #power-domain-cells = <1>;

      dpi-bridge {
        compatible = "nxp,imx93-pdfc";

        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          port@0 {
            reg = <0>;

            pdfc_from_lcdif: endpoint {
              remote-endpoint = <&lcdif_to_pdfc>;
            };
          };

          port@1 {
            reg = <1>;

            pdfc_to_panel: endpoint {
              remote-endpoint = <&panel_from_pdfc>;
              bus-width = <18>;
            };
          };
        };
      };
    };