// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree Source for AST27xx SoC Family
 *
 * Copyright (C) 2026 ASPEED Technology Inc.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "aspeed,ast2700";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x2>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x3>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2>;
		};

		l2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <1024>;
		};
	};

	secondary {
		#address-cells = <1>;
		#size-cells = <0>;

		ssp_nvic: interrupt-controller@e000e100 {
			compatible = "arm,v7m-nvic";
			#interrupt-cells = <2>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0xe000e100>;
			arm,num-irq-priority-bits = <3>;
			status = "disabled";
		};
	};

	tertiary {
		#address-cells = <1>;
		#size-cells = <0>;

		tsp_nvic: interrupt-controller@e000e100 {
			compatible = "arm,v7m-nvic";
			#interrupt-cells = <2>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0xe000e100>;
			arm,num-irq-priority-bits = <3>;
			status = "disabled";
		};
	};

	bootmcu {
		bootmcu_hlic: interrupt-controller {
			compatible = "riscv,cpu-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			status = "disabled";
		};
	};

	firmware {
		optee: optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};

		psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		atf: trusted-firmware-a@430000000 {
			reg = <0x4 0x30000000 0x0 0x80000>;
			no-map;
		};

		optee_core: optee-core@430080000 {
			reg = <0x4 0x30080000 0x0 0x1000000>;
			no-map;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a35-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
		arm,cpu-registers-not-fw-configured;
		always-on;
	};

	gic: interrupt-controller@12200000 {
		compatible = "arm,gic-v3";
		reg = <0 0x12200000 0 0x10000>, /* GICD */
		      <0 0x12280000 0 0x80000>, /* GICR */
		      <0 0x40440000 0 0x1000>;  /* GICC */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		#interrupt-cells = <3>;
		interrupt-controller;
	};

	soc0: bus@10000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x4000000>;
	};

	soc1: bus@14000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x0 0x14000000 0x0 0x14000000 0x2 0xec000000>;
	};
};

#include "aspeed-g7-soc0.dtsi"
#include "aspeed-g7-soc1.dtsi"