/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Device Tree binding constants for AST2700 reset controller.
 *
 * Copyright (c) 2024 Aspeed Technology Inc.
 */

#ifndef _MACH_ASPEED_AST2700_RESET_H_
#define _MACH_ASPEED_AST2700_RESET_H_

/* SOC0 */
#define SCU0_RESET_SDRAM	0
#define SCU0_RESET_DDRPHY	1
#define SCU0_RESET_RSA		2
#define SCU0_RESET_SHA3		3
#define SCU0_RESET_HACE		4
#define SCU0_RESET_SOC		5
#define SCU0_RESET_VIDEO	6
#define SCU0_RESET_2D		7
#define SCU0_RESET_PCIS		8
#define SCU0_RESET_RVAS0	9
#define SCU0_RESET_RVAS1	10
#define SCU0_RESET_SM3		11
#define SCU0_RESET_SM4		12
#define SCU0_RESET_CRT0		13
#define SCU0_RESET_ECC		14
#define SCU0_RESET_DP_PCI	15
#define SCU0_RESET_UFS		16
#define SCU0_RESET_EMMC		17
#define SCU0_RESET_PCIE1RST	18
#define SCU0_RESET_PCIE1RSTOE	19
#define SCU0_RESET_PCIE0RST	20
#define SCU0_RESET_PCIE0RSTOE	21
#define SCU0_RESET_JTAG		22
#define SCU0_RESET_MCTP0	23
#define SCU0_RESET_MCTP1	24
#define SCU0_RESET_XDMA0	25
#define SCU0_RESET_XDMA1	26
#define SCU0_RESET_H2X1		27
#define SCU0_RESET_DP		28
#define SCU0_RESET_DP_MCU	29
#define SCU0_RESET_SSP		30
#define SCU0_RESET_H2X0		31
#define SCU0_RESET_PORTA_VHUB	32
#define SCU0_RESET_PORTA_PHY3	33
#define SCU0_RESET_PORTA_XHCI	34
#define SCU0_RESET_PORTB_VHUB	35
#define SCU0_RESET_PORTB_PHY3	36
#define SCU0_RESET_PORTB_XHCI	37
#define SCU0_RESET_PORTA_VHUB_EHCI	38
#define SCU0_RESET_PORTB_VHUB_EHCI	39
#define SCU0_RESET_UHCI		40
#define SCU0_RESET_TSP		41
#define SCU0_RESET_E2M0		42
#define SCU0_RESET_E2M1		43
#define SCU0_RESET_VLINK	44

/* SOC1 */
#define SCU1_RESET_LPC0		0
#define SCU1_RESET_LPC1		1
#define SCU1_RESET_MII		2
#define SCU1_RESET_PECI		3
#define SCU1_RESET_PWM		4
#define SCU1_RESET_MAC0		5
#define SCU1_RESET_MAC1		6
#define SCU1_RESET_MAC2		7
#define SCU1_RESET_ADC		8
#define SCU1_RESET_SD		9
#define SCU1_RESET_ESPI0	10
#define SCU1_RESET_ESPI1	11
#define SCU1_RESET_JTAG1	12
#define SCU1_RESET_SPI0		13
#define SCU1_RESET_SPI1		14
#define SCU1_RESET_SPI2		15
#define SCU1_RESET_I3C0		16
#define SCU1_RESET_I3C1		17
#define SCU1_RESET_I3C2		18
#define SCU1_RESET_I3C3		19
#define SCU1_RESET_I3C4		20
#define SCU1_RESET_I3C5		21
#define SCU1_RESET_I3C6		22
#define SCU1_RESET_I3C7		23
#define SCU1_RESET_I3C8		24
#define SCU1_RESET_I3C9		25
#define SCU1_RESET_I3C10	26
#define SCU1_RESET_I3C11	27
#define SCU1_RESET_I3C12	28
#define SCU1_RESET_I3C13	29
#define SCU1_RESET_I3C14	30
#define SCU1_RESET_I3C15	31
#define SCU1_RESET_MCU0		32
#define SCU1_RESET_MCU1		33
#define SCU1_RESET_H2A_SPI1	34
#define SCU1_RESET_H2A_SPI2	35
#define SCU1_RESET_UART0	36
#define SCU1_RESET_UART1	37
#define SCU1_RESET_UART2	38
#define SCU1_RESET_UART3	39
#define SCU1_RESET_I2C_FILTER	40
#define SCU1_RESET_CALIPTRA	41
#define SCU1_RESET_XDMA		42
#define SCU1_RESET_FSI		43
#define SCU1_RESET_CAN		44
#define SCU1_RESET_MCTP		45
#define SCU1_RESET_I2C		46
#define SCU1_RESET_UART6	47
#define SCU1_RESET_UART7	48
#define SCU1_RESET_UART8	49
#define SCU1_RESET_UART9	50
#define SCU1_RESET_LTPI0	51
#define SCU1_RESET_VGAL		52
#define SCU1_RESET_LTPI1	53
#define SCU1_RESET_ACE		54
#define SCU1_RESET_E2M		55
#define SCU1_RESET_UHCI		56
#define SCU1_RESET_PORTC_USB2UART	57
#define SCU1_RESET_PORTC_VHUB_EHCI	58
#define SCU1_RESET_PORTD_USB2UART	59
#define SCU1_RESET_PORTD_VHUB_EHCI	60
#define SCU1_RESET_H2X		61
#define SCU1_RESET_I3CDMA	62
#define SCU1_RESET_PCIE2RST	63

#endif  /* _MACH_ASPEED_AST2700_RESET_H_ */