)]}'
{
  "commit": "42ecf7e48e6890ea5c6b4c5bdf954f0483ceecd9",
  "tree": "b17a7fc76bec16106632ffee752d9fb5a1c52745",
  "parents": [
    "649e144242b127a1fca3298cbceaa60dc04fc40a"
  ],
  "author": {
    "name": "Jake Chiang",
    "email": "hung-tse.chiang@fii-na.corp-partner.google.com",
    "time": "Thu Aug 13 13:35:03 2026 +0800"
  },
  "committer": {
    "name": "Jake Chiang",
    "email": "hung-tse.chiang@fii-na.corp-partner.google.com",
    "time": "Fri Aug 14 08:17:33 2026 -0700"
  },
  "message": "kernel: SRCREV bump 15e3ed4..dd52df9\n\nBilly Tsai (2):\n    arm64: dts: aspeed: reserve per-instance DMA pools for i3c HCI\n    i3c: mipi-i3c-hci: bind DMA rings to the reserved-memory pool\n\nJake Chiang (2):\n    arm64: dts: aspeed: adjust I3C HCI reserved memory layout\n    i3c: mipi-i3c-hci: dma: allocate IBI data before IBI status\n\nTested: Built\n\nGoogle-Bug-Id: 542414147\nChange-Id: I75eebddeac6d30c6e242a85ab83d5869c76f1da0\nSigned-off-by: Jake Chiang \u003chung-tse.chiang@fii-na.corp-partner.google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "cc1f771f51ce3d26cad115a6c664b908f75dcf04",
      "old_mode": 33188,
      "old_path": "recipes-kernel/linux/linux-gbmc_aspeedg7.bb",
      "new_id": "31c691b459cccfd66786d903b37e5a59e7096157",
      "new_mode": 33188,
      "new_path": "recipes-kernel/linux/linux-gbmc_aspeedg7.bb"
    }
  ]
}