tree b17a7fc76bec16106632ffee752d9fb5a1c52745
parent 649e144242b127a1fca3298cbceaa60dc04fc40a
author Jake Chiang <hung-tse.chiang@fii-na.corp-partner.google.com> 1786599303 +0800
committer Jake Chiang <hung-tse.chiang@fii-na.corp-partner.google.com> 1786720653 -0700

kernel: SRCREV bump 15e3ed4..dd52df9

Billy Tsai (2):
    arm64: dts: aspeed: reserve per-instance DMA pools for i3c HCI
    i3c: mipi-i3c-hci: bind DMA rings to the reserved-memory pool

Jake Chiang (2):
    arm64: dts: aspeed: adjust I3C HCI reserved memory layout
    i3c: mipi-i3c-hci: dma: allocate IBI data before IBI status

Tested: Built

Google-Bug-Id: 542414147
Change-Id: I75eebddeac6d30c6e242a85ab83d5869c76f1da0
Signed-off-by: Jake Chiang <hung-tse.chiang@fii-na.corp-partner.google.com>