)]}'
{
  "commit": "6e6376c68a59ed5703cba008bb9f083042c34d95",
  "tree": "d212ebdbc9b9a79bf15fa2daa12f9c533e50170b",
  "parents": [
    "9ac2e5f726db0a8e6ca0c36fd48e36e8a0216e46"
  ],
  "author": {
    "name": "James Zheng",
    "email": "alphetis@google.com",
    "time": "Tue Sep 08 21:32:54 2026 +0000"
  },
  "committer": {
    "name": "James Zheng",
    "email": "alphetis@google.com",
    "time": "Tue Sep 08 23:26:52 2026 -0700"
  },
  "message": "gbmcweb master: SRCREV bump dc357ba8f1..3c072ee195\n\ngBMC Team (3):\n      Support uint64_t Bus and Address properties for RawEeproms.\n      Integrate BIOS configuration updates into memory capacity registry operations.\n      Disable cached PWM writes in tlBMC Thermal Control\n\nFusion-Link: fusion2 N/A\nTested: fusion2.corp.google.com/a713be96-5be8-309b-812f-fe0f138fec25\nGoogle-Bug-Id: 541287798\nGoogle-Bug-Id: 545704112\nGoogle-Bug-Id: 558424309\nChange-Id: I67d837b142392cace776fe859d7019da208e1b19\nSigned-off-by: James Zheng \u003calphetis@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a2a4c29a01567ffbe20a4b0301b6c5c01e7eb9da",
      "old_mode": 33188,
      "old_path": "recipes-phosphor/interfaces/gbmcweb.inc",
      "new_id": "9f2266e5123184c0713c3b5cfe03eaf35c47d802",
      "new_mode": 33188,
      "new_path": "recipes-phosphor/interfaces/gbmcweb.inc"
    }
  ]
}