)]}'
{
  "id": "d3fb3abe0aa87dc4f01a2d9fa8da6c5628d786a2",
  "entries": [
    {
      "mode": 33188,
      "type": "blob",
      "id": "e354fd52c1dc21a54f5b9dab2ea18416e852b655",
      "name": "README.md"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "131b740bfce62284ac3f6987282f4b40081c154d",
      "name": "fpga-controller.c"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "d6bd7415f807e25ef4c926bb07c2ef8d96718bfb",
      "name": "fpga-controller.h"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "50ef41ba0301c5b5552c8abb862c19bf5925a9c4",
      "name": "fpga-maps.c"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "2cbf1392b675a6a72788dcd0b23d0785fa8e2631",
      "name": "fpga-maps.h"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "193509a0255ff4c9198e923531a40faaf04ecf8f",
      "name": "fpga-rules-lp30-dimm.c"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "978af9ec5e1742eee20d4c0a7f643fdf5bdd4e1d",
      "name": "fpga-rules-lp30-dimm.rows"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "f68ed0a79d41028a07f0899bf15bb6a0343ffc86",
      "name": "fpga-rules-lp30-links.c"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "2159c6a0daa06138d9b35ab4dc54cab338461437",
      "name": "fpga-rules-lp30-links.rows"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "dff7e29deff2bc8caa4cff3f6d96a4373141d8bd",
      "name": "fpga-rules-lp30-optics.c"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "020453baf47989aadff284c6222e981c37ba8352",
      "name": "fpga-rules-lp30-optics.rows"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "2f7c81c5b6a5b83dc04d9b21289b769c217810aa",
      "name": "fpga-rules-lp30-pdb.c"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "7bae821829555c87f0e526cc4207ee5cd876afdb",
      "name": "fpga-rules-lp30-pdb.rows"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "440c631ee66b152d1c80880100fd39ecb2c2c8df",
      "name": "fpga-rules-lp30-sdm.c"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "9cd39dd6ecb9f1ae7f718a5fde24a35f4e429e4e",
      "name": "fpga-rules-lp30-sdm.rows"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "dfe53a5f4c69d278177403a841c14c75e164d959",
      "name": "fpga-rules-lp30.c"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "09d52967fdfb6c2884630c56d7d41fe0eae0b5c6",
      "name": "fpga-rules-lp30.rows"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "71f58effadfb2f8046ca603c63e520c5953fa7a7",
      "name": "fpga-run.c"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "feda6b9aadfac5a0e607a123298d3ab9a613476c",
      "name": "fpga-run.h"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "86301ac7d26a552bc266edc2be3b3827e1762bf0",
      "name": "fpga-tables.c"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "0452f82f54245a29783a27fae2ce9b3a93d7285e",
      "name": "fpga-tables.h"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "9d0d2e9f7cb82ae32adedd0f5a9003821446958d",
      "name": "gen-fpga-rules.py"
    }
  ]
}
