)]}' { "commit": "64bf499edcd63c30199a1d46fc01e53570cbcfae", "tree": "7d9125d552c84cb612fee03b8bb9e96c5cf56250", "parents": [ "a4a8d1c3c4ebc52063397d4b7278a569d88f335a" ], "author": { "name": "Surya Garimella", "email": "sgarimella@nvidia.com", "time": "Mon Sep 14 09:43:39 2026 -0700" }, "committer": { "name": "Surya Garimella", "email": "sgarimella@nvidia.com", "time": "Thu Sep 17 21:37:33 2026 -0700" }, "message": "meta-hgxr: nsmd/libnsm TAV Mode Index 20 binding\n\nAdd libnsm NSM Type 5 Device Mode Index 20 (TAV Mode) codec\nsupport and the nsmd QTM4 handler/D-Bus binding, structurally\nmirroring the merged Power Capping Index 27 implementation.\n\nByte layout (enum8: Default\u003d0/Enabled\u003d1/Disabled\u003d2, 1-byte\npayload) mirrors Index 27 structurally and by value assignment.\nNo written NSM Index 20 contract exists yet -- this is a\nbest-effort mirror per engineer instruction and must be\nverified against a written NSM API contract before this ships.\n\nChanges:\n- libnsm/device-configuration.h: DEVICE_MODE_TAV \u003d 20,\n nsm_tav_mode enum, TAV_MODE_DATA_SIZE, with caveat comments.\n- libnsm/test/libnsm_device_configuration_test.cpp: tavModeV2\n suite mirroring powerCappingModeV2.\n- nsmd/nsmDeviceInventory/nsmSwitch.hpp/.cpp: NsmSwitchTAVMode\n sensor class, toTAVModeFromGet, genRequestMsg,\n handleResponseMsg, setTAVMode, createNsmSwitchTAVMode, gated\n on entity-manager SupportTAVMode in createNsmSwitchDI.\n- nsmd/nsmDeviceInventory/test/nsmSwitchFactoryBranch_test.cpp:\n TAVMode test block mirroring PowerCappingMode coverage.\n- nsmtool/nsm_config_cmd.cpp: GetTAVMode/SetTAVMode subcommands.\n\nDepends on PDI DGXOPENBMC-28636 (com.nvidia.DeviceMode.TAVMode)\nfor the generated server.hpp header used by nsmSwitch.hpp.\n\nReview fixups applied:\n- Removed internal ticket-ID references and \"mirrors power\n capping\" style comments from public source/header/test\n comments (kept the technical rationale).\n- SupportTAVMode gate now reads via the existing\n dbusPropertyMapAsBool helper instead of a raw\n std::get_if\u003cbool\u003e, so an integer-encoded EM value is\n normalized instead of silently resolving to false.\n- createNsmSwitchTAVMode kept inline (not static), matching\n the established file-local factory-helper convention used by\n createNsmSwitchPowerCappingMode and\n createNsmSwitchL1PredictionMode in this file.\n- GetTAVMode::parseResponseMsg rejects a missing/short\n CurrentMode instead of silently omitting it, matching the\n GetLTXMode/GetUPhyMode mandatory-CurrentMode convention.\n- Do not resolve Default on D-Bus publish: nsmd does not\n resolve a wire Default (0) CurrentMode/PendingMode to a\n guessed Enabled before publishing to D-Bus, on either the\n GET path or after a successful reset-to-default Set. No\n written contract or arch sign-off confirms what TAV\u0027s\n default actually is; the design doc only says it comes from\n QM4\u0027s own INI configuration, and the identical guess-on-\n mirror pattern was already wrong once for UPhy mode (commit\n c7c3b2b4). nsmd now publishes the wire value as-is; bmcweb\u0027s\n TAVMode handlers already treat a still-Default\n CurrentMode/PendingMode as not-yet-resolved by firmware,\n matching the existing LTXMode/UPhyRecoveryMode contract.\n\nNote: the nsmtool GetTAVMode CLI display intentionally still\nprints raw \"Default\" for wire value 0 (not \"Enabled\"),\nmatching the established GetPowerCappingMode/GetLTXMode/\nGetUPhyMode CLI precedent in this file. A prior review\ncomment suggested mapping Default to Enabled in the CLI to\nmatch D-Bus read semantics, but that no longer applies now\nthat nsmd does not resolve Default to Enabled on the D-Bus\nside either -- see the note above. Flagging for tech-lead\ncall rather than reintroducing the guess.\n\nTest status: local build blocked in this environment by a\nmissing dbus-1 pkg-config dependency (nsmtool/meson.build);\nclang-format-20 clean on all changed files. No lab/unit run\nperformed -- pending CI and PDI MR merge.\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-28638\n\nSigned-off-by: Surya Garimella \u003csgarimella@nvidia.com\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "8d2304248a1b57a4bfd0bdac1e434ae0273bf078", "old_mode": 33188, "old_path": "libnsm/device-configuration.h", "new_id": "d7956fd5b58b513b368464b9a5226af4cdef08e3", "new_mode": 33188, "new_path": "libnsm/device-configuration.h" }, { "type": "modify", "old_id": "781fa89ea59b8f81a63e9f92fa9ba168a4ce4d98", "old_mode": 33188, "old_path": "libnsm/test/libnsm_device_configuration_test.cpp", "new_id": "394595bb07a0f50ece7aa6a562f860d41ddd80ff", "new_mode": 33188, "new_path": "libnsm/test/libnsm_device_configuration_test.cpp" }, { "type": "modify", "old_id": "48dc929dffbe1aae1afa37c1a8d4a82c9703a87c", "old_mode": 33188, "old_path": "nsmd/nsmDeviceInventory/nsmSwitch.cpp", "new_id": "d8a31c253c75f070c1512ff8b29bad2eb799aa26", "new_mode": 33188, "new_path": "nsmd/nsmDeviceInventory/nsmSwitch.cpp" }, { "type": "modify", "old_id": "18c869bb89ea08237a425be17746da0139584753", "old_mode": 33188, "old_path": "nsmd/nsmDeviceInventory/nsmSwitch.hpp", "new_id": "42281cd8cbe09b183cee1f1da9bd51cd69757c7e", "new_mode": 33188, "new_path": "nsmd/nsmDeviceInventory/nsmSwitch.hpp" }, { "type": "modify", "old_id": "cda22b3493ae21001a1f25715729f27d645eb89d", "old_mode": 33188, "old_path": "nsmd/nsmDeviceInventory/test/nsmSwitchFactoryBranch_test.cpp", "new_id": "ace8a8f0d2ecd1b2012b1c5054c04b86e9720d06", "new_mode": 33188, "new_path": "nsmd/nsmDeviceInventory/test/nsmSwitchFactoryBranch_test.cpp" }, { "type": "modify", "old_id": "378641ed11d7cb507c27c8924a304bfafc466c43", "old_mode": 33188, "old_path": "nsmtool/nsm_config_cmd.cpp", "new_id": "994bb683fe84973765103010a1a3482e927b1724", "new_mode": 33188, "new_path": "nsmtool/nsm_config_cmd.cpp" }, { "type": "modify", "old_id": "e13896730e62daa4f56086f333e7973081d6275e", "old_mode": 33188, "old_path": "nsmtool/test/nsm_config_cmd_branch_test.cpp", "new_id": "81bf083db61cf11d055fe47428b599c0b5807c90", "new_mode": 33188, "new_path": "nsmtool/test/nsm_config_cmd_branch_test.cpp" } ] }