)]}' { "log": [ { "commit": "62de34e8b8bda9eab592ad737b7fbb3924a55e89", "tree": "ded9a1848c51a7dbcfe4c250bc85cc78787b52ef", "parents": [ "3547cc7e233ef9cb81cfb8f09b854f600258928c" ], "author": { "name": "Raziel Lopez", "email": "raziellopez@google.com", "time": "Tue Sep 23 19:51:41 2025 +0000" }, "committer": { "name": "Raziel Lopez", "email": "raziellopez@google.com", "time": "Tue Sep 23 23:17:02 2025 +0000" }, "message": "MCTP requester, solve Internal Compiler Error for g++ 13.2\n\nCreate intermediate DBus interface object and use it for\nthe coGetServiceMap awaitable object creation to avoid ICE.\n\nGoogle-Bug-Id: 437731307\nChange-Id: Ib0f12413e99f83db3e02ca71bfca55edd9045942\nSigned-off-by: Raziel Lopez \u003craziellopez@google.com\u003e\n" }, { "commit": "3547cc7e233ef9cb81cfb8f09b854f600258928c", "tree": "b0119790b7c389ded9a80d4649864ce06d500a22", "parents": [ "571d9ae0ac343191e8d3b51b55350ff28cbd97e0" ], "author": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Mon Sep 15 12:35:43 2025 -0700" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Mon Sep 15 13:30:41 2025 -0700" }, "message": "Surround NVIDIA_SHMEM for relevant code\n\nThis file was missing NVIDIA_SHMEM protection while including the shared\nmemory header file sharedMemCommon.hpp\n\nGoogle-Bug-Id: 437731307\nChange-Id: I212bb5b341bb3bdaa3087badbc5fce2b7a46067d\nSigned-off-by: Akshat Jain \u003cakshatzen@google.com\u003e\n" }, { "commit": "571d9ae0ac343191e8d3b51b55350ff28cbd97e0", "tree": "81bda5b4bdb87d6f2d4784a55173060e8ffe97a5", "parents": [ "f9c283392dafeaf80c8c8cb372382a60cd2391f3" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Fri Aug 22 17:12:02 2025 +0530" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Tue Sep 02 16:49:27 2025 -0700" }, "message": "Meson option for enabling cx8 features\n\nNOTE: Testing is not done for flag cx8-feature-flag.\n\nmeson: make sources conditional per module\n\n- nsmd: disable all subdirs by default; always include nsmRawCommand,\nnsmLongRunning, nsmEvent, nsmSetAsync\n- nsmPort: keep infra always; gate ports via -Dnsm-port-include /\n-Dnsm-port-all\n- nsmChassis: keep core; gate features via -Dnsm-chassis-include /\n-Dnsm-chassis-all\n- nsmDeviceInventory: keep nsmSwitch; gate others via\n-Dnsm-device-inventory-include / -Dnsm-device-inventory-all\n- nsmEvent: only LongRunning by default; others via -Dnsm-event-include\n/ -Dnsm-event-all\n- nsmSetAsync: only infra by default; ops via -Dnsm-set-async-include /\n-Dnsm-set-async-all\n- add nsmd-subdir-* feature flags to opt-in per subdir\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nmeson: conditionalize modules and centralize subdir control\n\nmeson: validate include lists and warn on unknown tokens\n\n- nsmPort: warn on unknown nsm-port-include entries\n- nsmEvent: warn on unknown nsm-event-include entries\n- nsmSetAsync: warn on unknown nsm-set-async-include entries\n- nsmChassis: warn on unknown nsm-chassis-include entries\n- nsmDeviceInventory: warn on unknown nsm-device-inventory-include\nentries\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nmeson: add libnsm conditional inclusion with validation\n\n- Add -Dlibnsm-all (default true) and -Dlibnsm-include\u003d... array\n- Always include base.c, instance-id.c, requester/mctp.c\n- Gate remaining libnsm modules via options; warn on unknown tokens\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nmeson: gate libnsm sources; drop legacy adapter flag; add nsmSensors\nconditional inclusion\n\n- libnsm: add \u0027network-ports\u0027 token; gate modules via -Dlibnsm-include /\n-Dlibnsm-all\n- nsmd: move network-ports.c and pci-links.c under libnsm gating; remove\nfrom nsmPort\n- nsmDeviceInventory: drop \u0027nsm-network-adapter\u0027 in favor of\n-Dnsm-device-inventory-include\u003dnetwork-adapter; gate nsmSwitch.cpp via\n\u0027switch\u0027 token\n- nsmSensors: add -Dnsm-sensors-include / -Dnsm-sensors-all and warn on\nunknown tokens\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nmeson(nsmd): centralize subdir control via nsmd-subdirs-all and\nnsmd-subdirs-include\n\n- Remove per-subdir nsmd-subdir-* options\n- Validate nsmd-subdirs-include entries\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nmeson(nsmDbusIfaceOverride): add conditional inclusion via\n-Dnsm-dbus-override-include / -Dnsm-dbus-override-all\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nmeson(nsmChassis): gate nsmChassis.cpp under \u0027chassis-core\u0027 token\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nmeson: correct options for ports\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nFormatting meson\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nChange default value to true for all subdir include\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nRefactor ErrorInjection and PCieGroups\n\n- relocate nsmErrorInjectionCommon.hpp\n- update includes and meson\n- remove old sensor wiring\n- move NsmPciGroup2/3/4 test to common suite\n- Move NsmPcieGroup base and NsmPciGroup2/3/4 to nsmCommon\n- Extract NsmPciePortIntf to nsmCommon\n- Update includes and meson sources\n- Remove redundant includes in retimer/gpu pcie port\n- No logic/flow changes\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nmeson: add cx8-features profile option\n\n- Add boolean option cx8-features\n- When enabled, set per-module includes:\n nsmd-subdirs, chassis, sensors, dbus-override,\n device-inventory, ports\n- When enabled, set libnsm modules to:\n device-capability-discovery, platform-environmental, pci-links\n network-ports\n- Force-disable debug-token, debug-info, histogram, and error-injection\n macros under profile\n- Wire overrides in nsmd and module meson.build files\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nAdded missing nsmDeviceInventory\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nAdded knob for enable-network-adapter-reset\n\nFixed meson.build for cx8-features\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nFixed meson.build for cx8-feature for pcie device\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-19233\n\nChange-Id: I828f01b7139f2c8d69400c7fcba12e8ee55d90b3\n" }, { "commit": "f9c283392dafeaf80c8c8cb372382a60cd2391f3", "tree": "dfe3aaa4e96bebf2d18e6b10b59b720659a3311d", "parents": [ "77fa2427490c96e5a9d0304e430ca4c5701412cb" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Thu Aug 14 13:31:29 2025 +0530" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Tue Sep 02 16:49:23 2025 -0700" }, "message": "Make NVIDIA shared memory (shmem) feature optional\n\nadding conditional compilation guards around shmem-related headers,\nmaking the shmem feature optional in build configurations, and\nchanging the default value from enabled to disabled.\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-18776\n\nChange-Id: Ic6ac5005c2bfe32885132a9d5f85677f62520910\n" }, { "commit": "77fa2427490c96e5a9d0304e430ca4c5701412cb", "tree": "dabf9097b01c34e8458fc8f8b8253470fb3f6a15", "parents": [ "ddd967569b1ff479c41c25eef6ea54637d53f352" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Thu Aug 14 09:41:06 2025 +0530" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Tue Sep 02 16:49:16 2025 -0700" }, "message": "Removed unnecessary includes from headers\n\nFixes compilation issues with shared memory api\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-18776\n\nChange-Id: I3f26efea4d694618a651e115da7dc1ce04c8675a\n" }, { "commit": "ddd967569b1ff479c41c25eef6ea54637d53f352", "tree": "dfe3aaa4e96bebf2d18e6b10b59b720659a3311d", "parents": [ "fa26b342fe85a7b5c7bfade1fe1a7f015adfe51d" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Fri Aug 08 13:11:38 2025 +0200" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Tue Sep 02 16:49:11 2025 -0700" }, "message": "Refactor DeviceManager and Mctp Discovery for Coroutine Management\n\nThis commit enhances the coroutine management in the DeviceManager\nclass by replacing raw coroutine handles with a new\n`requester::Coroutine` class. It simplifies the handling of device\ndiscovery and update tasks, improving code clarity and maintainability.\nAdditionally, it removes the now-unnecessary coroutine handles from the\nheader file.\n\nFixes JIRA https://\nChange-Id: I80835f930426798b753f509e7d6f360295160874\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "fa26b342fe85a7b5c7bfade1fe1a7f015adfe51d", "tree": "2b048eb8e2bc095dc46351a535c3672b95af6ba4", "parents": [ "2734b812763991117d7f79ecd6d07b6ad5faa5c0" ], "author": { "name": "Ayush Kumar Thakur", "email": "ayushkumart@nvidia.com", "time": "Mon Jun 30 20:05:55 2025 +0530" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Tue Sep 02 16:48:51 2025 -0700" }, "message": "Refactor Static Inventory, MCTP Discovery and Rediscovery Flow\n\n\u0027\u0027\u0027\nwhy:\n1. NsmDevice was created based on static inventory provided by EM config file and it was mapped to the MCTP EID in sensor polling loop.\n This was not an efficient and cleaner method to remap device and there was dependency on sensor manager to map EID from Static inventory.\n2. The MCTP rediscovery flow was not efficient, leading to many incoming bugs in field. There was multiple in between operations involved in\n MCTP rediscovery signal and the corresponding nsmDevice going online and offline.\n3. Due to issue 2, it was creating hindrance in making discovery flow atomic.\n\nwhat:\n1. Restructuring of static inventory object in EM config file, it will help in removing instance mapping file from platform configs.\n2. MCTP discovery/Rediscovery flow and Static inventory mapping is restructured and made more modular.\n\u0027\u0027\u0027\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n\nRefactor Init, Mctp Rediscovery and Synchronize Post/Patch\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n\nFix for state maintenance during rediscovery and state management\n\n\u0027\u0027\u0027\n- Implement sequential processing of rediscovery signals\n- Add queue management for MCTP info in device manager\n- Update NsmDevice state based on queued MCTP info\n- Ensure state consistency with last received signal\n\u0027\u0027\u0027\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nsigned-off-by \u003cayushkumart@nvidia.com\u003e\n\nAdd Coroutine Semaphore for locking nsm device update\n\n\u0027\u0027\u0027\nSemaphore is required for synchronizing update nsm device during init if mctp discovery signal is also received.\n\u0027\u0027\u0027\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n\nRefactor: Extract capability sensor refresh into separate function\n\n\u0027\u0027\u0027\nCapability sensors must be refreshed after MCTP rediscovery events and driver reloads. Previously, this functionality was embedded within a monolithic function that also handled command code matrix refresh and FRU updates. This commit extracts the capability sensor refresh logic into a dedicated `refreshCapabilitySensor()` function to improve code modularity and maintainability.\n\nThe new function is called from:\n- MCTP rediscovery event handlers\n- Driver reload scenarios\n- Device state transitions\n\u0027\u0027\u0027\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n\nDefer Rediscovery Event processing while MCTP rediscovery is in progress\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n\nRebase after upstream sync\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n\nChange-Id: I2d87efe8a0b49ce5d3ee324aea89e9a50fc53e58\n" }, { "commit": "2734b812763991117d7f79ecd6d07b6ad5faa5c0", "tree": "dfe3aaa4e96bebf2d18e6b10b59b720659a3311d", "parents": [ "55779543abdc92c4a7bd150c2bc6a2f2a877310d" ], "author": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Wed Aug 20 15:44:48 2025 -0700" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Wed Aug 20 15:45:04 2025 -0700" }, "message": "NSM: Add libmctp-externals.h from Nvidia\u0027s repo\n\nWe need to add libmctp-externals.h library from Nvidia\u0027s libmctp repo\nhttps://github.com/NVIDIA/libmctp/blob/develop/libmctp-externals.h\n\nGoogle-Bug-Id: 437731307\nChange-Id: I44559f58a0337b093795231bb2532084a52a0ba2\nSigned-off-by: Akshat Jain \u003cakshatzen@google.com\u003e\n" }, { "commit": "55779543abdc92c4a7bd150c2bc6a2f2a877310d", "tree": "ffba488ac53f85fe7b6c3c9f3dbc917e0f4ecfe5", "parents": [ "222ca027920cbfb16e532b5b8fdd8c50d0cbe3d5" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Thu Aug 14 13:31:29 2025 +0530" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Mon Aug 18 16:41:03 2025 -0700" }, "message": "Make NVIDIA shared memory (shmem) feature optional\n\nadding conditional compilation guards around shmem-related headers,\nmaking the shmem feature optional in build configurations, and\nchanging the default value from enabled to disabled.\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-18776\nGoogle-Bug-Id: 437731307\nChange-Id: Ie1a6ef625abd720dff262bd581c705a0a9b05cc6\nSigned-off-by: Akshat Jain \u003cakshatzen@google.com\u003e\n" }, { "commit": "222ca027920cbfb16e532b5b8fdd8c50d0cbe3d5", "tree": "7c2c7e47f36e4b3e985524bc0b4a6b5506c87918", "parents": [ "d61c3c315a6f11f26f05c7484e69461efee8bd08" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Thu Aug 14 09:41:06 2025 +0530" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Mon Aug 18 16:40:50 2025 -0700" }, "message": "Removed unnecessary includes from headers\n\nFixes compilation issues with shared memory api\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-18776\nGoogle-Bug-Id: 437731307\nChange-Id: I1ffc393af5e2fb2a7e05ff3f60fe78131635740f\nSigned-off-by: Akshat Jain \u003cakshatzen@google.com\u003e\n" }, { "commit": "d61c3c315a6f11f26f05c7484e69461efee8bd08", "tree": "eb73329a83a897925351fd8480a950fa7b2616ca", "parents": [ "24a89e8a9294ec8ac664aa8234a2ea0cc00c2aa7" ], "author": { "name": "christianc", "email": "christianc@nvidia.com", "time": "Thu Jul 31 05:03:27 2025 +0000" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Mon Aug 18 16:40:42 2025 -0700" }, "message": "[meta-hgxb300] CX8 MultiPortPCIeSwitchDevice Support for v2 properties\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5387216\nGoogle-Bug-Id: 437731307\nChange-Id: I03ee245ae8182d4f63bde04eefcc030a7c09e2d1\nSigned-off-by: Akshat Jain \u003cakshatzen@google.com\u003e\nSigned-off by: Christian Choi \u003cchristianc@nvidia.com\u003e\n" }, { "commit": "24a89e8a9294ec8ac664aa8234a2ea0cc00c2aa7", "tree": "5322c734fd87d92ed434bbb87283aa4569cb3d93", "parents": [ "7d703f8b59fb7d9d80e2aa01126f6cdb6e7ce80e" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Thu Aug 07 15:15:56 2025 +0530" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Mon Aug 18 16:40:33 2025 -0700" }, "message": "Log flooding fix : Get Port Network Addresses\n\n```\nChanges :\nTest logs setup for dev debugging cleared due to log flooding\n\nFixes NVBug https://\n```\nGoogle-Bug-Id: 437731307\nChange-Id: I18c0b143c8452e8ff8eafd6d7e172878b391520f\nSigned-off-by: Akshat Jain \u003cakshatzen@google.com\u003e\n" }, { "commit": "7d703f8b59fb7d9d80e2aa01126f6cdb6e7ce80e", "tree": "c642c16907bf0d8e8c622b563064f88cea0fd774", "parents": [ "04c4c95a4524667b1679d73fb19535c069d222d3" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Fri Aug 08 13:11:38 2025 +0200" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Mon Aug 18 16:40:27 2025 -0700" }, "message": "Refactor DeviceManager and Mctp Discovery for Coroutine Management\n\nThis commit enhances the coroutine management in the DeviceManager\nclass by replacing raw coroutine handles with a new\n`requester::Coroutine` class. It simplifies the handling of device\ndiscovery and update tasks, improving code clarity and maintainability.\nAdditionally, it removes the now-unnecessary coroutine handles from the\nheader file.\n\nFixes JIRA https://\nGoogle-Bug-Id: 437731307\nChange-Id: I25fad7a4b50bbf223379c05e20060d454567991b\nSigned-off-by: Akshat Jain \u003cakshatzen@google.com\u003e\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "04c4c95a4524667b1679d73fb19535c069d222d3", "tree": "fcb882087d1bcfd758ec1ef22103305ddd15ca15", "parents": [ "3600b4285d2c36e9d5d6cdf7f2b4f73d50140bd7" ], "author": { "name": "Ayush Kumar Thakur", "email": "ayushkumart@nvidia.com", "time": "Mon Jun 30 20:05:55 2025 +0530" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Mon Aug 18 16:39:59 2025 -0700" }, "message": "Refactor Static Inventory, MCTP Discovery and Rediscovery Flow\n\n\u0027\u0027\u0027\nwhy:\n1. NsmDevice was created based on static inventory provided by EM config file and it was mapped to the MCTP EID in sensor polling loop.\n This was not an efficient and cleaner method to remap device and there was dependency on sensor manager to map EID from Static inventory.\n2. The MCTP rediscovery flow was not efficient, leading to many incoming bugs in field. There was multiple in between operations involved in\n MCTP rediscovery signal and the corresponding nsmDevice going online and offline.\n3. Due to issue 2, it was creating hindrance in making discovery flow atomic.\n\nwhat:\n1. Restructuring of static inventory object in EM config file, it will help in removing instance mapping file from platform configs.\n2. MCTP discovery/Rediscovery flow and Static inventory mapping is restructured and made more modular.\n\u0027\u0027\u0027\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n\nRefactor Init, Mctp Rediscovery and Synchronize Post/Patch\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n\nFix for state maintenance during rediscovery and state management\n\n\u0027\u0027\u0027\n- Implement sequential processing of rediscovery signals\n- Add queue management for MCTP info in device manager\n- Update NsmDevice state based on queued MCTP info\n- Ensure state consistency with last received signal\n\u0027\u0027\u0027\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nsigned-off-by \u003cayushkumart@nvidia.com\u003e\n\nAdd Coroutine Semaphore for locking nsm device update\n\n\u0027\u0027\u0027\nSemaphore is required for synchronizing update nsm device during init if mctp discovery signal is also received.\n\u0027\u0027\u0027\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n\nRefactor: Extract capability sensor refresh into separate function\n\n\u0027\u0027\u0027\nCapability sensors must be refreshed after MCTP rediscovery events and driver reloads. Previously, this functionality was embedded within a monolithic function that also handled command code matrix refresh and FRU updates. This commit extracts the capability sensor refresh logic into a dedicated `refreshCapabilitySensor()` function to improve code modularity and maintainability.\n\nThe new function is called from:\n- MCTP rediscovery event handlers\n- Driver reload scenarios\n- Device state transitions\n\u0027\u0027\u0027\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n\nDefer Rediscovery Event processing while MCTP rediscovery is in progress\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n\nRebase after upstream sync\n\nFixes Jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17745\nGoogle-Bug-Id: 437731307\nChange-Id: I24abe7c5d3a7f2148d348268f45f87e4493df691\nSigned-off-by: Akshat Jain \u003cakshatzen@google.com\u003e\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n" }, { "commit": "3600b4285d2c36e9d5d6cdf7f2b4f73d50140bd7", "tree": "e0b41d9433f6b6b6b98a96e7fd5ad0b8588bc199", "parents": [ "c9c80134396fb062fac4902f009bcd6c66da6dce" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Wed Aug 06 09:30:07 2025 +0200" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Mon Aug 18 16:39:44 2025 -0700" }, "message": "Fix sdbusplus compilation and update README\n\nPrevious sdbusplus commit was causing compilation issues with gcc14.\nUpdate to a newer revision that resolves these issues and ensures\ncompatibility with both gcc13 and gcc14 compilers. Also update README\nwith clearer instructions for libmctp header setup.\n\nFixes JIRA https://\nGoogle-Bug-Id: 437731307\nChange-Id: Id0ce76e8f7187a9fb23901168b8b304f44db86a2\nSigned-off-by: Akshat Jain \u003cakshatzen@google.com\u003e\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "c9c80134396fb062fac4902f009bcd6c66da6dce", "tree": "870ada4570788170ebcc5cbe1816e4fdcc518b95", "parents": [ "8471df2595f612f20475cf8fbd13f64bf6e11e3c" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Mon Jul 28 15:03:37 2025 +0200" }, "committer": { "name": "Akshat Jain", "email": "akshatzen@google.com", "time": "Mon Aug 18 16:36:47 2025 -0700" }, "message": "Enhance throttle reason handling in NsmProcessor\n\nAdded additional throttle reason updates for hardware slowdown,\nthermal slowdown, power brake slowdown, and sync boost in the\nNsmProcessorThrottleReason::updateReading function. This improves\nthe processor\u0027s performance interface by providing more detailed\nthrottle reasons.\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5328994\nGoogle-Bug-Id: 437731307\nChange-Id: I0b45471167c29385dee70b5bd93d965693655910\nSigned-off-by: Akshat Jain \u003cakshatzen@google.com\u003e\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "8471df2595f612f20475cf8fbd13f64bf6e11e3c", "tree": "15f646141ad6ed79fa95fe0b7301bad309b22105", "parents": [ "dee192c1fb13ca5f8e6692c6e6bef5cc9bb8b585" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Mon Jul 21 11:33:53 2025 +0200" }, "committer": { "name": "Pawel Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Mon Aug 04 22:46:03 2025 -0700" }, "message": "Optimize dbus communication for sensor readings\n\nThis commit introduces a new utility function\n`getCurrentSteadyClockTimestamp` to retrieve the current steady clock\ntimestamp in milliseconds. Additionally, it updates various sensor\nclasses to utilize this new function for timestamping sensor readings,\nensuring consistent and accurate time tracking across the system.\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-17812\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "dee192c1fb13ca5f8e6692c6e6bef5cc9bb8b585", "tree": "1efcc981cecb093b4265b24826f126d1305f5fb9", "parents": [ "d384d59245e82b77c7a0a99c14c4942452dde9a0" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Mon Jul 21 09:37:38 2025 +0200" }, "committer": { "name": "Pawel Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Mon Aug 04 22:46:03 2025 -0700" }, "message": "Refactor long-running sensor management in SensorManagerImpl\n\nThis commit refactors the long-running sensor handling in the\n`SensorManagerImpl` class. The `deviceLongRunningTask` method has been\nrenamed to `updateLongRunningSensor`, and its logic has been simplified\nto improve clarity and efficiency. Additionally, the polling logic has\nbeen updated to ensure proper coroutine management for long-running\nsensors.\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-17810\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "d384d59245e82b77c7a0a99c14c4942452dde9a0", "tree": "6eef56cce00acecbb45348af292fd16d06065794", "parents": [ "b0c1e14b20409d0c385debbc2443272837006e65" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Fri Jul 18 15:22:51 2025 +0200" }, "committer": { "name": "Pawel Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Mon Aug 04 22:46:03 2025 -0700" }, "message": "Enhance NsmDevice and SensorManagerImpl for improved sensor management\n\nThis commit introduces a new method `allCommandCodesAreRetrieved` in\nthe `NsmDevice` class to check if all command codes have been retrieved.\nIt also refactors the sensor management logic, replacing raw vectors\nwith a `SensorQueue` structure for better organization of sensor types.\nAdditionally, it updates the polling logic in `SensorManagerImpl` to\nutilize the new sensor management approach.\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-17810\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "b0c1e14b20409d0c385debbc2443272837006e65", "tree": "e0631d71ca31217b74dbe3fc1a69ba0634431a49", "parents": [ "9079fd8fc6e7643b262dad819ec6d33b5500a133" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Fri Jul 18 16:17:15 2025 +0200" }, "committer": { "name": "Pawel Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Mon Aug 04 22:46:03 2025 -0700" }, "message": "Refactor, coroutine handling and improve README instructions\n\nThis commit enhances the coroutine management in the `NsmDevice` and\n`SensorManagerImpl` classes by replacing raw coroutine handles with a\nnew `requester::Coroutine` class. Additionally, it updates the README\nfile to include instructions for installing missing pip modules and\napt libraries, and it adds a command to copy the latest `libmctp-externals.h`\nto the common directory.\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-17810\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "9079fd8fc6e7643b262dad819ec6d33b5500a133", "tree": "880a16f52e7dc578c9fa6e6ed6591f87d1e90359", "parents": [ "eac361015ce6d6cd03f67f5fc112bf1051f0e906" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Thu Jul 17 11:52:58 2025 +0200" }, "committer": { "name": "Pawel Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Mon Aug 04 22:46:03 2025 -0700" }, "message": "Removed unused PollingState enum and GlobalPollingStateManager class\n\nThis commit eliminates the `PollingState` enum and the\n`GlobalPollingStateManager` class, as they are no longer needed\nin the current implementation. Additionally, references to\npolling state management have been removed from the `NsmDevice`\nand `SensorManagerImpl` classes.\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-17810\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "eac361015ce6d6cd03f67f5fc112bf1051f0e906", "tree": "3dab74a2cf7811e258da1025bdf1499a8f882e07", "parents": [ "50e961bd0fb198db2f4fd93ecbdf35d70c3cf79f" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Mon Aug 04 16:52:46 2025 +0530" }, "committer": { "name": "Aishwary Joshi", "email": "aishwaryj@nvidia.com", "time": "Mon Aug 04 10:34:40 2025 -0700" }, "message": "Fix coverity issue with mock\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-17802\n" }, { "commit": "50e961bd0fb198db2f4fd93ecbdf35d70c3cf79f", "tree": "92d6ee694c27712e3ce6e4fe45073f8c3e70a022", "parents": [ "014aae917af25fca3326f7a2d6e0c539c073ba6e" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Mon Aug 04 15:39:37 2025 +0530" }, "committer": { "name": "Aishwary Joshi", "email": "aishwaryj@nvidia.com", "time": "Mon Aug 04 10:34:40 2025 -0700" }, "message": "FRU object to be created once\n\n- Create and recreate fru only when invnetory info change\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17802\n" }, { "commit": "014aae917af25fca3326f7a2d6e0c539c073ba6e", "tree": "b2f1a705771daed8fdf0d636952398b5f8446959", "parents": [ "3df60bf2bfa7e3b4f82e7b840299d12b57a0bad9" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Thu Jul 31 20:22:16 2025 +0530" }, "committer": { "name": "Aishwary Joshi", "email": "aishwaryj@nvidia.com", "time": "Mon Aug 04 10:34:40 2025 -0700" }, "message": "Formatting changes with \"Clang-19\"\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-1628\n" }, { "commit": "3df60bf2bfa7e3b4f82e7b840299d12b57a0bad9", "tree": "e79f2e4fa38d434814ffbbf92e2d93c93d2e03ab", "parents": [ "258a430a7822f14e3d609371bff15d66ff7338cd" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Fri Jul 18 00:34:55 2025 +0530" }, "committer": { "name": "Aishwary Joshi", "email": "aishwaryj@nvidia.com", "time": "Mon Aug 04 10:34:40 2025 -0700" }, "message": "fix test nsmChassis, nsmProcessor, nsmPort etc\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-1628\n" }, { "commit": "258a430a7822f14e3d609371bff15d66ff7338cd", "tree": "3122a3f1ee172b9a9299b326979fe42ad5f107a5", "parents": [ "ba64fc58dfb7c916ab75307d5e90fb78aa3eed54" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Thu Jul 17 17:09:09 2025 +0530" }, "committer": { "name": "Aishwary Joshi", "email": "aishwaryj@nvidia.com", "time": "Mon Aug 04 10:34:40 2025 -0700" }, "message": "Formatting changes\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-1628\n" }, { "commit": "ba64fc58dfb7c916ab75307d5e90fb78aa3eed54", "tree": "bd2684bf4f1beeb505de08b881bc74b89a43c956", "parents": [ "a9b15e7cd5b9a24ca46814c803223af32a489340" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Thu Jul 17 12:29:04 2025 +0530" }, "committer": { "name": "Aishwary Joshi", "email": "aishwaryj@nvidia.com", "time": "Mon Aug 04 10:34:40 2025 -0700" }, "message": "Refactor D-Bus operations and implement async logging\n\n- Migrated all D-Bus interfaces from get to getAll for\n better performance\n- Implemented async logging functionality with logEventAsync()\n to prevent blocking\n- Added coroutine-based D-Bus utilities in dBusAsyncUtils.hpp\n- Added service caching for D-Bus operations to reduce lookup\n overhead\n- Updated event handling to use fire-and-forget async logging\n pattern\n- Modified multiple components: chassis, events, inventory\n sensors, ports, processors\n- Enhanced requester utilities for better async operation\n support\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-1628\n" }, { "commit": "a9b15e7cd5b9a24ca46814c803223af32a489340", "tree": "1b805f9ea8cf8704b5d1f88c1bd4eb9f9dc4ce50", "parents": [ "767132733c3388745c0bc02ff61006cdf295d5f5" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Tue Jul 08 19:51:36 2025 +0530" }, "committer": { "name": "Aishwary Joshi", "email": "aishwaryj@nvidia.com", "time": "Mon Aug 04 10:34:40 2025 -0700" }, "message": "migrate nsmChassis from get to getAll\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-16283\n" }, { "commit": "767132733c3388745c0bc02ff61006cdf295d5f5", "tree": "85c20922095ff5da2a509b1dc80df7854f5f41a4", "parents": [ "17b3ac6f7711058ad764b9a86bee05ef912818aa" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Mon Jul 07 17:23:57 2025 +0530" }, "committer": { "name": "Aishwary Joshi", "email": "aishwaryj@nvidia.com", "time": "Mon Aug 04 10:34:40 2025 -0700" }, "message": "test change to support coGetAllProperty\n\nFixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-16283\n" }, { "commit": "17b3ac6f7711058ad764b9a86bee05ef912818aa", "tree": "3c84d555671cd7c0b8dca97c003205e25b13a9b5", "parents": [ "b0a0f58c7f518a59c87298c46e20858e8ecca1fc" ], "author": { "name": "Ayush Kumar Thakur", "email": "ayushkumart@nvidia.com", "time": "Thu Jul 31 12:26:58 2025 +0530" }, "committer": { "name": "svcdgx", "email": "group_3005_bot_871b8a89a193009b5d6a6b2fa1d60393@noreply.gitlab-master.nvidia.com", "time": "Mon Aug 04 02:23:05 2025 -0700" }, "message": "Fix data type of EID in rediscovery flow\n\n\u0027\u0027\u0027\nThe data type of EID has changed on mctp from uint32_t to uint8_t. This was breaking mctp rediscovery flow.\nThis commit will be fixing the issue.\n\n\u0027\u0027\u0027\n\nFixes nvbug https://\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n" }, { "commit": "b0a0f58c7f518a59c87298c46e20858e8ecca1fc", "tree": "ca3afaccda667a0e6874766e92cfd23d0fd518d5", "parents": [ "06c0cc84c0f705635b2318276b7e65c97734889f" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Sat Aug 02 18:35:10 2025 +0200" }, "committer": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Sat Aug 02 20:06:16 2025 +0200" }, "message": "Update README with Meson build configuration and debugging instructions\n\n- Enhanced Meson build configuration section with detailed debug options\n and compiler flags.\n- Added new section for debugging unit tests using GDB in console and\n VSCode/Cursor, including configuration examples for launch.json and\n tasks.json.\n\nFixes JIRA https://\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "06c0cc84c0f705635b2318276b7e65c97734889f", "tree": "b89df10e104d3e509c6d249805adb704fdfbc511", "parents": [ "dc5f390b44e58cf078d71a4ff6bb992b52b7cc7d" ], "author": { "name": "Surya Garimella", "email": "sgarimella@nvidia.com", "time": "Tue Jul 29 14:37:14 2025 -0700" }, "committer": { "name": "Surya Deepak Garimella", "email": "sgarimella@nvidia.com", "time": "Thu Jul 31 11:12:25 2025 -0700" }, "message": "meta-hgxb300: Fix for ProcessorMetrics Bandwidthpercent\n\nThis fix is based on the telemetry catalog expectation\nthat indicates that processorMetrics#BandwidthPercent\nand ProcessorMetrics#SMUtilizationPercent should be the\nSM Util Percent.\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5394164\n\nSigned-off-by: Surya Garimella \u003csgarimella@nvidia.com\u003e\n" }, { "commit": "dc5f390b44e58cf078d71a4ff6bb992b52b7cc7d", "tree": "f19b682ca06c0933937bbd5979089f82e6954bf7", "parents": [ "a950d51969609826a8bc0be2835e894aee7ba6bc" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Mon Jul 28 12:55:04 2025 +0200" }, "committer": { "name": "Pawel Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Thu Jul 31 01:30:23 2025 -0700" }, "message": "Update README to reflect installation of clang-format-19 for CI usage\n\nChanges:\n- Updated installation instructions from clang-format-17 to\n clang-format-19.\n- Adjusted usage instructions to match the new version.\n\nFixes JIRA https://\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "a950d51969609826a8bc0be2835e894aee7ba6bc", "tree": "544621ffcadcd26f3371a884743f401b50c66fd4", "parents": [ "fc91e6842e807781053a9b70d9aa78caab714116" ], "author": { "name": "Kshitiz", "email": "kshitizk@nvidia.com", "time": "Thu Jul 31 11:51:35 2025 +0530" }, "committer": { "name": "Kshitiz", "email": "kshitizk@nvidia.com", "time": "Thu Jul 31 12:23:21 2025 +0530" }, "message": "nsmd : fix out of bounds access\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5397590\n\nSigned-off-by: Kshitiz . \u003ckshitizk@nvidia.com\u003e\n" }, { "commit": "fc91e6842e807781053a9b70d9aa78caab714116", "tree": "5196958003c0e86529b0d013f2be5fdc97da626e", "parents": [ "cec1e4081c74ef1e6445a9ff1fdd9087b3c59d93" ], "author": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Tue Jul 29 19:10:06 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Wed Jul 30 15:42:21 2025 +0530" }, "message": "nsmd : select mctp eid based on the binding\n\nIf an endpoint has multiple mctp eids, select the eid whose binding\noffers higher bandwidth\n\nTested.\n\nBoth eid 10 (HMC ERoT SPI) and 15 (HMC ERoT USB) are discovered, but\nonly eid 15 is used.\n\n```\nroot@gb200nvl-hmc:~# busctl tree xyz.openbmc_project.NSM\n|- /ResetStatistics\n`- /xyz\n `- /xyz/openbmc_project\n |- /xyz/openbmc_project/FruDevice\n | |- /xyz/openbmc_project/FruDevice/12\n | |- /xyz/openbmc_project/FruDevice/13\n | |- /xyz/openbmc_project/FruDevice/15\n | |- /xyz/openbmc_project/FruDevice/16\n | |- /xyz/openbmc_project/FruDevice/18\n | |- /xyz/openbmc_project/FruDevice/19\n | |- /xyz/openbmc_project/FruDevice/20\n | |- /xyz/openbmc_project/FruDevice/21\n | |- /xyz/openbmc_project/FruDevice/24\n | |- /xyz/openbmc_project/FruDevice/26\n | `- /xyz/openbmc_project/FruDevice/27\n |- /xyz/openbmc_project/NSM\n | `- /xyz/openbmc_project/NSM/Raw\n |- /xyz/openbmc_project/inventory\n | `- /xyz/openbmc_project/inventory/system\n | |- /xyz/openbmc_project/inventory/system/HGX_Module_0_SPI\n | |- /xyz/openbmc_project/inventory/system/accelerator\n | | |- /xyz/openbmc_project/inventory/system/accelerator/Diagnostics\n\nroot@gb200nvl-hmc:~# journalctl -u nsmd -b | grep -i \u0027found nsm\u0027\nJul 30 09:20:19 gb200nvl-hmc nsmd[1466]: found NSM device, eid\u003d10 uuid\u003df72d6fa0-5675-11ed-9b6a-0242ac120002\nJul 30 09:20:19 gb200nvl-hmc nsmd[1466]: found NSM device, eid\u003d12 uuid\u003dc01dc250-5678-11ed-9b6a-0242ac120002\nJul 30 09:20:19 gb200nvl-hmc nsmd[1466]: found NSM device, eid\u003d13 uuid\u003df72d6f50-5675-11ed-9b6a-0242ac120002\nJul 30 09:20:19 gb200nvl-hmc nsmd[1466]: found NSM device, eid\u003d15 uuid\u003df72d6fa0-5675-11ed-9b6a-0242ac120002\nJul 30 09:20:19 gb200nvl-hmc nsmd[1466]: found NSM device, eid\u003d16 uuid\u003df72d6f60-5675-11ed-9b6a-0242ac120002\nJul 30 09:20:48 gb200nvl-hmc nsmd[1466]: found NSM device, eid\u003d20 uuid\u003dc01dc251-5678-11ed-9b6a-0242ac120002\nJul 30 09:20:48 gb200nvl-hmc nsmd[1466]: found NSM device, eid\u003d21 uuid\u003df72d6f51-5675-11ed-9b6a-0242ac120002\nJul 30 09:20:48 gb200nvl-hmc nsmd[1466]: found NSM device, eid\u003d24 uuid\u003df72d6f61-5675-11ed-9b6a-0242ac120002\nJul 30 09:21:00 gb200nvl-hmc nsmd[1466]: found NSM device, eid\u003d18 uuid\u003df72d6fb0-5675-11ed-9b6a-0242ac120002\nJul 30 09:21:00 gb200nvl-hmc nsmd[1466]: found NSM device, eid\u003d19 uuid\u003df72d6fb1-5675-11ed-9b6a-0242ac120002\nJul 30 09:21:00 gb200nvl-hmc nsmd[1466]: found NSM device, eid\u003d26 uuid\u003df72d6fb2-5675-11ed-9b6a-0242ac120002\nJul 30 09:21:00 gb200nvl-hmc nsmd[1466]: found NSM device, eid\u003d27 uuid\u003df72d6fb3-5675-11ed-9b6a-0242ac120002\n\nroot@gb200nvl-hmc:~# journalctl -u nsmd -b | grep \u0027doPollingTask: found\u0027\nJul 30 09:20:52 gb200nvl-hmc nsmd[1466]: doPollingTask: found EID:15 by searchEID for nsmDevice(4,0,0)\nJul 30 09:20:52 gb200nvl-hmc nsmd[1466]: doPollingTask: found EID:16 by searchEID for nsmDevice(4,3,0)\nJul 30 09:20:52 gb200nvl-hmc nsmd[1466]: doPollingTask: found EID:24 by searchEID for nsmDevice(4,4,0)\nJul 30 09:20:52 gb200nvl-hmc nsmd[1466]: doPollingTask: found EID:13 by searchEID for nsmDevice(4,1,0)\nJul 30 09:20:52 gb200nvl-hmc nsmd[1466]: doPollingTask: found EID:21 by searchEID for nsmDevice(4,2,0)\nJul 30 09:20:52 gb200nvl-hmc nsmd[1466]: doPollingTask: found EID:12 by searchEID for nsmDevice(3,0,0)\nJul 30 09:20:52 gb200nvl-hmc nsmd[1466]: doPollingTask: found EID:20 by searchEID for nsmDevice(3,1,0)\nJul 30 09:21:00 gb200nvl-hmc nsmd[1466]: doPollingTask: found EID:26 by searchEID for nsmDevice(0,2,0)\nJul 30 09:21:00 gb200nvl-hmc nsmd[1466]: doPollingTask: found EID:18 by searchEID for nsmDevice(0,0,0)\nJul 30 09:21:00 gb200nvl-hmc nsmd[1466]: doPollingTask: found EID:19 by searchEID for nsmDevice(0,1,0)\nJul 30 09:21:00 gb200nvl-hmc nsmd[1466]: doPollingTask: found EID:27 by searchEID for nsmDevice(0,3,0)\n```\n\nfixes JIRA https://\n\nSigned-off-by: Harshit Aghera \u003chaghera@nvidia.com\u003e\n" }, { "commit": "cec1e4081c74ef1e6445a9ff1fdd9087b3c59d93", "tree": "0a4d1e221d26b57adb4913dbb08d782d55c31649", "parents": [ "a8a6cd6cff4284546bb463b92834830599809166" ], "author": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Tue Jul 29 20:03:14 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Tue Jul 29 20:03:14 2025 +0530" }, "message": "nsmd : fix ci failures\n\nfixes JIRA https://\n\nSigned-off-by: Harshit Aghera \u003chaghera@nvidia.com\u003e\n" }, { "commit": "a8a6cd6cff4284546bb463b92834830599809166", "tree": "96c5246d7fb399a1d20a0e4a64b3867c0afa0f4c", "parents": [ "8f5b6c92420b2bf28133e08d84b37b45ee3a55cb" ], "author": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Tue Jul 29 19:25:17 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Tue Jul 29 19:25:17 2025 +0530" }, "message": "nsmd : select eid to filter\n\nadd configuration option to select which mctp eid to filter\n\nfixes JIRA https://\n\nSigned-off-by: Harshit Aghera \u003chaghera@nvidia.com\u003e\n" }, { "commit": "8f5b6c92420b2bf28133e08d84b37b45ee3a55cb", "tree": "92f5b885393e2db28b6587161c371d6ce1d4a552", "parents": [ "624ab826991ca1d5d7ecd65487736acb2eed5cc0", "b097d3659ddb66bbd86a4d00371334c7ca20fce1" ], "author": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 12:34:22 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 13:09:28 2025 +0530" }, "message": "Merge branch develop-next\n\nMigrate to CodeConstruct MCTP Daemon\n\nfixes JIRA https://\n\nSigned-off-by: Harshit Aghera \u003chaghera@nvidia.com\u003e\n" }, { "commit": "b097d3659ddb66bbd86a4d00371334c7ca20fce1", "tree": "f400c1be2a3c9c07f9636d39a1bc025b4774e0ca", "parents": [ "d3b03e58ec05606189e6a6c71236c05557cf3302" ], "author": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 11:39:17 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 11:39:17 2025 +0530" }, "message": "fix compilation errors\n\nfixes JIRA https://\n\nSigned-off-by: Harshit Aghera \u003chaghera@nvidia.com\u003e\n" }, { "commit": "d3b03e58ec05606189e6a6c71236c05557cf3302", "tree": "f6ae1243f2d85e758c0df09e1dc41a1e9879521f", "parents": [ "884a1d7587c825fea855a34aab5ce568297d608c" ], "author": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 11:16:32 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 11:17:03 2025 +0530" }, "message": "fix formatting\n\nfixes JIRA https://\n\nSigned-off-by: Harshit Aghera \u003chaghera@nvidia.com\u003e\n" }, { "commit": "884a1d7587c825fea855a34aab5ce568297d608c", "tree": "181684588692110b021a015d1768f9967d6cc866", "parents": [ "90d3dccdf34c31e2c183cd62ecb9154ed9fef1df" ], "author": { "name": "raghulr", "email": "raghulr@ami.com", "time": "Mon Jun 23 23:51:57 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Adding shmem update for new MRD\n\nfixes nvbug https://nvbugs/5122931\n\nSigned-off-by: raghul r \u003craghulr@ami.com\u003e\n" }, { "commit": "90d3dccdf34c31e2c183cd62ecb9154ed9fef1df", "tree": "5d9e0684de9b57e8c90ad4a5f3fcab38b585dba5", "parents": [ "a2126ed1f99c7ff4773f1645ab19276b80e7062d" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Wed Jul 16 10:53:13 2025 +0200" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Refactor driver version handling in GPUSWInventory\n\nChanges:\n- Updated driverVersion to use std::string for better memory\n management.\n- Adjusted error handling to set previous driver version on\n failure.\n- Improved state change detection and logging for driver state\n updates.\n\nTested enabling/disabling persistence mode on all 8 GPUs using\nnvidia-smi on umb-emr-410. Verified driver state transitions through\nRedfish API on HMC; all GPUs correctly reported Enabled or Disabled\nafter each state change. Repeated the enable cycle again to confirm\nstability and consistent reporting.\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5351720\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "a2126ed1f99c7ff4773f1645ab19276b80e7062d", "tree": "e29f31a42d50763e49aa738d7080320d1d5cdf17", "parents": [ "2e7c861a241ed9d70267746b3d2829b1e819d972" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Tue Jul 15 16:40:40 2025 +0200" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Fixed unexpected dump AllowableValues for HGXB300\n\nUpdated the nsmChassisCreateSensors function to correctly add\nstatic sensors for the NSM_DeviceDiagnostics type. This change\nensures proper handling of device diagnostics within the\nNVIDIA chassis management system.\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5180657\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "2e7c861a241ed9d70267746b3d2829b1e819d972", "tree": "50728e05eb3216093c5e54eda2f851293120df5f", "parents": [ "f84710f12dff4cf00bb3e7f0a3b42bb965f24a0f" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Thu Jun 26 15:13:03 2025 +0200" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Optimized diagnostics handling\n\nThis commit introduces a new `TimeMeasureLogger` class for logging\nexecution time of various operations. It also refactors the existing\ndiagnostics handling in the `NsmDebugInfoObject` and related classes\nto utilize this new logging mechanism. The `NsmDeviceDiagnostics`\nclass has been removed as its functionality is now integrated into\n`NsmDebugInfoObject`.\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-16346\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "f84710f12dff4cf00bb3e7f0a3b42bb965f24a0f", "tree": "57c4b5560f996adf91499837badd9c8b4fd4e027", "parents": [ "ad6ba2b732bf93cd1f49b9c4617aaf76261f2435" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Thu Jul 10 08:32:42 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Added UTs for get Port ECC Counterso\n\n```\nChanges:\n- Added UTs for decode/encode req/resp functions\n- port number size changed to 16 bits\n- get port ecc counters sensor enabled\n\nFixes JIRA https://jirasw.nvidia.com/browse/iDGXOPENBMC-15778\n```\n" }, { "commit": "ad6ba2b732bf93cd1f49b9c4617aaf76261f2435", "tree": "7c7aed8a14b768d456d0dc3d298bbd4eff5cf989", "parents": [ "a3dd5c9721d3cd095aee665c970150106e1f9fb1" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Tue May 20 15:26:25 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Added shmem support for get port ecc counters\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "a3dd5c9721d3cd095aee665c970150106e1f9fb1", "tree": "242946dfc39e4d1c3634a1d4253ee2ee9060c997", "parents": [ "d78901551206b9033decc361e5c5a7c924420f84" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Tue May 20 07:27:59 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Added Get Port ECC Counters Sensor support\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "d78901551206b9033decc361e5c5a7c924420f84", "tree": "567d543aaeb1460cf0744df744759f6af87de350", "parents": [ "78832c2f4bcd8c1e7233a6f16bca56acb7ce36c3" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Mon May 19 21:52:39 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Added mockupResponder support for Get Port ECC Counters\n\nFixes NVBug https://nvbugspro.nvidia.com/bug/5104921\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "78832c2f4bcd8c1e7233a6f16bca56acb7ce36c3", "tree": "d975b0cd0d1a45450aeecfa6b2786ef37090ac86", "parents": [ "d62c26e9c8acfb7a9ad5b908b1a0b406471b554d" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Mon May 19 21:51:08 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Added encode/decode functions for Get Port ECC Counters\n\nFixes NVBug https://nvbugspro.nvidia.com/bug/5104921\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "d62c26e9c8acfb7a9ad5b908b1a0b406471b554d", "tree": "a9e279eb431a78ebd6e0c34740d598db3a8d46fa", "parents": [ "20fb475ee5feeb8193b2bf9fd64e201466f6e89c" ], "author": { "name": "Harsh Verma", "email": "harshv@nvidia.com", "time": "Wed Jul 16 04:32:24 2025 -0700" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Added NSM Type 1 API getNetworkAddresses support\n\n\n```\nChanges include:\n\n1. getNetworkAddresses request msg encode and decode functions\n2. getNetworkAddresses aggregate response msg sample encode and decode functions\n3. nsm raw command support for getNetworkAddresses\n4. nsmMockupResponder support for mock aggregate response\n5. getNetworkAddresses aggregate sensor implementation\n6. Added new dbus paths and associations for port network identifiers : Ethernet MAC Address , Permanent MAC Address , Node GUID\n```\n\n\nAddressing comments for Get Port Network Addresses support\n\n```\nchanges:\n1. updated UTs, added new cases\n2. remove endian conversion for mac address (collection data type)\n3. updated network address object path associations , aligned with design doc\n```\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15794\n" }, { "commit": "20fb475ee5feeb8193b2bf9fd64e201466f6e89c", "tree": "9b477efd08fd770af43b8b5439684e304c47de08", "parents": [ "e300ed2eaba0e8330a96e052588dc65449dd8464" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Wed Jul 16 09:42:04 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Fix UTs for Get Ethernet Port Counters Request\n\n```\nChanges :\n- Fixes UTs for encode/decodeEthPortTelemetryCounterReq to align with comments\n addressed in commit 2777a0915c8b5b5016a1c621791a0e92a8974a2e\n```\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "e300ed2eaba0e8330a96e052588dc65449dd8464", "tree": "0964c793c75d1d2713d164988001f17cdc150140", "parents": [ "25b60f3382f7c2a6e7602ea2d0b1aed8586df61e" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Mon Jul 07 20:04:25 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Addressing comments for Eth Port Counters Support\n\n```\nChanges :\n- Updated decode/encode resp functions to handle data of different types\n- Updated decode/encode req functions : change portNumber data size\n- added size checks to mockupResponder response creation\n```\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "25b60f3382f7c2a6e7602ea2d0b1aed8586df61e", "tree": "088a6ad1d6dc9107dcee695094f29d9b5db60451", "parents": [ "734df509058ba54a87acb18c8a9a2d72d9e37096" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Mon May 19 13:27:53 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Addressing comments for Eth Port Counters aggregate sensor\n\n```\nChanges :\n- Added NSM_GET_ETH_PORT_TELEMETRY_COUNTER to supported commands in mockupResponder\n- Fixed EthPortTelemetryAggregator intialization\n- removed filler comments\n- Updated NSMPortMetrics implementation to align with new PDI\n- Updated NSM_GET_ETH_PORT_TELEMETRY_COUNTER command code\n```\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "734df509058ba54a87acb18c8a9a2d72d9e37096", "tree": "d54103eb6b94ed57abe719f25acc4e295bf65546", "parents": [ "e267d64f6fe55f1e93b0c254471cbf2a7d3cbc78" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Thu Apr 03 14:34:15 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Added Aggregate sensor for get ethernet port counters\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "e267d64f6fe55f1e93b0c254471cbf2a7d3cbc78", "tree": "3cd1e4769b212c846c284251e547fee6d12aefb7", "parents": [ "5a424c58af21fe1e8e238026e2c9e4863ad6415e" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Mon Mar 10 14:53:17 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Added MockupResponder for Ethernet Port Telemetry Counters\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "5a424c58af21fe1e8e238026e2c9e4863ad6415e", "tree": "17a10deff8c793bbee236f3fe847155ae56b5d54", "parents": [ "8b402e057a28bee2f3bffcbd8a61a97e57baca77" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Mon Mar 10 15:16:47 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:13 2025 +0530" }, "message": "Added encode/decode functions for Ethernet Port Telemetry Counters\n\n Fixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "8b402e057a28bee2f3bffcbd8a61a97e57baca77", "tree": "cc47b737d8e56a8cdcc904678040325f989c79d6", "parents": [ "00e919c7a1fc16516d3322dea696235954c12566" ], "author": { "name": "raghulr", "email": "raghulr@ami.com", "time": "Mon Jun 30 20:29:27 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:08 2025 +0530" }, "message": "Adding support to MCU reset boot reasons\n\nfixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-18081\n\nSome more new MCU reset/boot reason are added support on NSM spec.\nThis commit adding support to get all boot reason bit fields\n(256 bits) and decode that values to update it on dbus\nbootreason property.\n\nSigned-off-by: raghul r \u003craghulr@ami.com\u003e\n" }, { "commit": "00e919c7a1fc16516d3322dea696235954c12566", "tree": "85b33a757230931338c4b46bb51de3daa0705f18", "parents": [ "05a0cfdb8a43c86d8af5ac8c4d7330f99b6fa8e6" ], "author": { "name": "Karthick Sundarrajan", "email": "ksundarrajan@nvidia.com", "time": "Thu Jul 10 03:21:58 2025 -0700" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:08 2025 +0530" }, "message": "Add support for type-2 PCIeDevice group0 telemetry\n\nAdded type-2 support for GROUP_ID_0 and GROUP_ID_1 to populate\nPCIeDevice telemetry.\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5306349\n\nTested:\n```\nroot@hgxb300:~# busctl introspect \"xyz.openbmc_project.NSM\" \"/xyz/openbmc_project/inventory/system/chassis/HGX_ConnectX_0/PCIeDevices/ConnectX_0\" --full\nNAME TYPE SIGNATURE RESULT/VALUE FLAGS\norg.freedesktop.DBus.Introspectable interface - - -\n.Introspect method - s -\norg.freedesktop.DBus.Peer interface - - -\n.GetMachineId method - s -\n.Ping method - - -\norg.freedesktop.DBus.Properties interface - - -\n.Get method ss v -\n.GetAll method s a{sv} -\n.Set method ssv - -\n.PropertiesChanged signal sa{sv}as - -\nxyz.openbmc_project.Association.Definitions interface - - -\n.Associations property a(sss) 1 \"chassis\" \"pciedevice\" \"/xyz/openbmc_project/inventory/system/chassis/HGX_ConnectX_0\" emits-change writable\nxyz.openbmc_project.Common.UUID interface - - -\n.UUID property s \"ae0a96c0-cb06-11e5-a837-3c6d669340f0\" emits-change writable\nxyz.openbmc_project.Inventory.Decorator.Asset interface - - -\n.BuildDate property s \"0000-00-00T00:00:00Z\" emits-change writable\n.Manufacturer property s \"NVIDIA\" emits-change writable\n.Model property s \"Nvidia ConnectX8 XDR IB/800GBE for Nvidia B300 NVL8 ------- System\" emits-change writable\n.Name property s \"NA\" emits-change writable\n.PartNumber property s \"MLX000647\" emits-change writable\n.SKU property s \"NA\" emits-change writable\n.SerialNumber property s \"1662425750916\" emits-change writable\n.SparePartNumber property s \"\" emits-change writable\n.SubModel property s \"\" emits-change writable\nxyz.openbmc_project.Inventory.Item.PCIeDevice interface - - -\n.DeviceType property s \"SingleFunction\" emits-change writable\n.Function0ClassCode property s \"0x000000\" emits-change writable\n.Function0DeviceClass property s \"ProcessingAccelerators\" emits-change writable\n.Function0DeviceId property s \"0x1023\" emits-change writable\n.Function0FunctionType property s \"Physical\" emits-change writable\n.Function0RevisionId property s \"0x00\" emits-change writable\n.Function0SubsystemId property s \"0x0101\" emits-change writable\n.Function0SubsystemVendorId property s \"0x15B3\" emits-change writable\n.Function0VendorId property s \"0x15B3\" emits-change writable\n.Function1ClassCode property s \"\" emits-change writable\n...\n...\n.Function7VendorId property s \"\" emits-change writable\n.GenerationInUse property s \"xyz.openbmc_project.Inventory.Item.PCIeSlot.Generations.Gen5\" emits-change writable\n.GenerationSupported property s \"xyz.openbmc_project.Inventory.Item.PCIeSlot.Generations.Unknown\" emits-change writable\n.LanesInUse property u 16 emits-change writable\n.MaxLanes property u 16 emits-change writable\n.MaxPCIeType property s \"xyz.openbmc_project.Inventory.Item.PCIeDevice.PCIeTypes.Gen5\" emits-change writable\n.PCIeType property s \"xyz.openbmc_project.Inventory.Item.PCIeDevice.PCIeTypes.Gen5\" emits-change writable\nxyz.openbmc_project.State.Decorator.Health interface - - -\n.Health property s \"xyz.openbmc_project.State.Decorator.Health.HealthType.OK\" emits-change writable\nroot@hgxb300:~# busctl introspect \"xyz.openbmc_project.NSM\" \"/xyz/openbmc_project/inventory/system/chassis/HGX_NVLinkManagementNIC_0/PCIeDevices/NVLinkManagementNIC_0\" --full\nNAME TYPE SIGNATURE RESULT/VALUE FLAGS\norg.freedesktop.DBus.Introspectable interface - - -\n.Introspect method - s -\norg.freedesktop.DBus.Peer interface - - -\n.GetMachineId method - s -\n.Ping method - - -\norg.freedesktop.DBus.Properties interface - - -\n.Get method ss v -\n.GetAll method s a{sv} -\n.Set method ssv - -\n.PropertiesChanged signal sa{sv}as - -\nxyz.openbmc_project.Association.Definitions interface - - -\n.Associations property a(sss) 1 \"chassis\" \"pciedevice\" \"/xyz/openbmc_project/inventory/system/chassis/HGX_NVLinkManagementNIC_0\" emits-change writable\nxyz.openbmc_project.Common.UUID interface - - -\n.UUID property s \"ae0a96c0-cb06-11e5-a837-3c6d669340ec\" emits-change writable\nxyz.openbmc_project.Inventory.Decorator.Asset interface - - -\n.BuildDate property s \"0000-00-00T00:00:00Z\" emits-change writable\n.Manufacturer property s \"NVIDIA\" emits-change writable\n.Model property s \"Nvidia ConnectX7 mezz for Nvidia B300 NVL8 --------System\" emits-change writable\n.Name property s \"NA\" emits-change writable\n.PartNumber property s \"V000S4N03X\" emits-change writable\n.SKU property s \"NA\" emits-change writable\n.SerialNumber property s \"1662425750916\" emits-change writable\n.SparePartNumber property s \"\" emits-change writable\n.SubModel property s \"\" emits-change writable\nxyz.openbmc_project.Inventory.Decorator.PCIeRefClock interface - - -\n.PCIeReferenceClockCount property t 0 emits-change\n.PCIeReferenceClockEnabled property b false emits-change\nxyz.openbmc_project.Inventory.Item.PCIeDevice interface - - -\n.DeviceType property s \"SingleFunction\" emits-change writable\n.Function0ClassCode property s \"0x000000\" emits-change writable\n.Function0DeviceClass property s \"ProcessingAccelerators\" emits-change writable\n.Function0DeviceId property s \"0x1021\" emits-change writable\n.Function0FunctionType property s \"Physical\" emits-change writable\n.Function0RevisionId property s \"0x00\" emits-change writable\n.Function0SubsystemId property s \"0x1113\" emits-change writable\n.Function0SubsystemVendorId property s \"0x15B3\" emits-change writable\n.Function0VendorId property s \"0x15B3\" emits-change writable\n.Function1ClassCode property s \"\" emits-change writable\n...\n...\n.Function7VendorId property s \"\" emits-change writable\n.GenerationInUse property s \"xyz.openbmc_project.Inventory.Item.PCIeSlot.Generations.Gen3\" emits-change writable\n.GenerationSupported property s \"xyz.openbmc_project.Inventory.Item.PCIeSlot.Generations.Unknown\" emits-change writable\n.LanesInUse property u 2 emits-change writable\n.MaxLanes property u 2 emits-change writable\n.MaxPCIeType property s \"xyz.openbmc_project.Inventory.Item.PCIeDevice.PCIeTypes.Gen4\" emits-change writable\n.PCIeType property s \"xyz.openbmc_project.Inventory.Item.PCIeDevice.PCIeTypes.Gen3\" emits-change writable\nxyz.openbmc_project.State.Chassis interface - - -\n.CurrentPowerState property s \"xyz.openbmc_project.State.Chassis.PowerState.On\" emits-change writable\n.CurrentPowerStatus property s \"xyz.openbmc_project.State.Chassis.PowerStatus.Undefined\" emits-change writable\n.LastStateChangeTime property t 0 emits-change writable\n.RequestedPowerTransition property s \"xyz.openbmc_project.State.Chassis.Transition.Off\" emits-change writable\nxyz.openbmc_project.State.Decorator.Health interface - - -\n.Health property s \"xyz.openbmc_project.State.Decorator.Health.HealthType.OK\" emits-change writable\nroot@hgxb300:~#\nroot@hgxb300:~# curl 192.168.31.1/redfish/v1/Chassis/HGX_ConnectX_0/PCIeDevices/ConnectX_0\n{\n \"@odata.id\": \"/redfish/v1/Chassis/HGX_ConnectX_0/PCIeDevices/ConnectX_0\",\n \"@odata.type\": \"#PCIeDevice.v1_14_0.PCIeDevice\",\n \"DeviceType\": \"SingleFunction\",\n \"Id\": \"ConnectX_0\",\n \"Links\": {\n \"Switch\": {\n \"@odata.id\": \"/redfish/v1/Fabrics/HGX_PCIeTopology_0/Switches/ConnectX_Switch_0\"\n }\n },\n \"Manufacturer\": \"NVIDIA\",\n \"Model\": \"Nvidia ConnectX8 XDR IB/800GBE for Nvidia B300 NVL8 ----- System\",\n \"Name\": \"PCIe Device\",\n \"Oem\": {\n \"Nvidia\": {\n \"@odata.type\": \"#NvidiaPCIeDevice.v1_2_0.NvidiaPCIeDevice\"\n }\n },\n \"PCIeFunctions\": {\n \"@odata.id\": \"/redfish/v1/Chassis/HGX_ConnectX_0/PCIeDevices/ConnectX_0/PCIeFunctions\"\n },\n \"PCIeInterface\": {\n \"LanesInUse\": 16,\n \"MaxLanes\": 16,\n \"MaxPCIeType\": \"Gen5\",\n \"PCIeType\": \"Gen5\"\n },\n \"PartNumber\": \"MLX000647\",\n \"SerialNumber\": \"1662425750916\",\n \"Status\": {\n \"Conditions\": [],\n \"Health\": \"OK\",\n \"HealthRollup\": \"OK\",\n \"State\": \"Enabled\"\n },\n \"UUID\": \"ae0a96c0-cb06-11e5-a837-3c6d669340f0\"\n}root@hgxb300:~#\nroot@hgxb300:~# curl 192.168.31.1/redfish/v1/Chassis/HGX_NVLinkManagementNIC_0/PCIeDevices/NVLinkManagementNIC_0\n{\n \"@odata.id\": \"/redfish/v1/Chassis/HGX_NVLinkManagementNIC_0/PCIeDevices/NVLinkManagementNIC_0\",\n \"@odata.type\": \"#PCIeDevice.v1_14_0.PCIeDevice\",\n \"DeviceType\": \"SingleFunction\",\n \"Id\": \"NVLinkManagementNIC_0\",\n \"Manufacturer\": \"NVIDIA\",\n \"Model\": \"Nvidia ConnectX7 mezz for Nvidia B300 NVL8 ---- System\",\n \"Name\": \"PCIe Device\",\n \"Oem\": {\n \"Nvidia\": {\n \"@odata.type\": \"#NvidiaPCIeDevice.v1_2_0.NvidiaPCIeDevice\",\n \"PCIeReferenceClockEnabled\": false\n }\n },\n \"PCIeFunctions\": {\n \"@odata.id\": \"/redfish/v1/Chassis/HGX_NVLinkManagementNIC_0/PCIeDevices/NVLinkManagementNIC_0/PCIeFunctions\"\n },\n \"PCIeInterface\": {\n \"LanesInUse\": 2,\n \"MaxLanes\": 2,\n \"MaxPCIeType\": \"Gen4\",\n \"PCIeType\": \"Gen3\"\n },\n \"PartNumber\": \"V000S4N03X\",\n \"SerialNumber\": \"1662425750916\",\n \"Status\": {\n \"Conditions\": [],\n \"Health\": \"OK\",\n \"HealthRollup\": \"OK\",\n \"State\": \"Enabled\"\n },\n \"UUID\": \"ae0a96c0-cb06-11e5-a837-3c6d669340ec\"\n}root@hgxb300:~#\n```\n```\n\nSigned-off-by: Karthick Sundarrajan \u003cksundarrajan@nvidia.com\u003e\n" }, { "commit": "05a0cfdb8a43c86d8af5ac8c4d7330f99b6fa8e6", "tree": "2f932c1fd5bc8fd7e4ddd76c9bb1c06374f8854d", "parents": [ "80a277fea7b013130b75b598d0ecba86677c577d" ], "author": { "name": "raghulr", "email": "raghulr@ami.com", "time": "Thu Jun 19 16:57:18 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 28 10:38:00 2025 +0530" }, "message": "Adding Hw version support for CX8 chassis\n\nfixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-17635\n\nNSM type-3 GetInventoryInformation property id 11 support\nHW version on connectX chassis resources.\n\nSigned-off-by: raghul r \u003craghulr@ami.com\u003e\n" }, { "commit": "624ab826991ca1d5d7ecd65487736acb2eed5cc0", "tree": "34df3ee0717121054fa5244618513644215c76fb", "parents": [ "e4939d950889e6052279a8ec18f21ca21f715e25" ], "author": { "name": "raghulr", "email": "raghulr@ami.com", "time": "Mon Jun 23 23:51:57 2025 +0530" }, "committer": { "name": "Raghul Rajakumar", "email": "rrajakumar@nvidia.com", "time": "Wed Jul 23 10:39:32 2025 -0700" }, "message": "Adding shmem update for new MRD\n\nfixes nvbug https://nvbugs/5122931\n\nSigned-off-by: raghulr \u003craghulr@ami.com\u003e\n" }, { "commit": "e4939d950889e6052279a8ec18f21ca21f715e25", "tree": "5a583b48a2e264c952f548538101d79fb395fea9", "parents": [ "2dd0e602a95dd42761c0055d459be10543591df4" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Wed Jul 16 10:53:13 2025 +0200" }, "committer": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Tue Jul 22 15:21:22 2025 +0200" }, "message": "Refactor driver version handling in GPUSWInventory\n\nChanges:\n- Updated driverVersion to use std::string for better memory\n management.\n- Adjusted error handling to set previous driver version on\n failure.\n- Improved state change detection and logging for driver state\n updates.\n\nTested enabling/disabling persistence mode on all 8 GPUs using\nnvidia-smi on umb-emr-410. Verified driver state transitions through\nRedfish API on HMC; all GPUs correctly reported Enabled or Disabled\nafter each state change. Repeated the enable cycle again to confirm\nstability and consistent reporting.\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5351720\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "2dd0e602a95dd42761c0055d459be10543591df4", "tree": "fde1530a6b5b48e98bdd595f11d15c58c99ba41a", "parents": [ "fc563f5ede7481c4d393985bc7026d502864905f" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Tue Jul 15 16:40:40 2025 +0200" }, "committer": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Thu Jul 17 13:17:35 2025 +0200" }, "message": "Fixed unexpected dump AllowableValues for HGXB300\n\nUpdated the nsmChassisCreateSensors function to correctly add\nstatic sensors for the NSM_DeviceDiagnostics type. This change\nensures proper handling of device diagnostics within the\nNVIDIA chassis management system.\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5180657\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "fc563f5ede7481c4d393985bc7026d502864905f", "tree": "d2084f3710d1113ba04e238fdbe02ec4dbe5fb45", "parents": [ "94ccc56d6b14925bc1723da47c2ccd0f8e7640ac" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Thu Jun 26 15:13:03 2025 +0200" }, "committer": { "name": "Pawel Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Wed Jul 16 09:35:17 2025 -0700" }, "message": "Optimized diagnostics handling\n\nThis commit introduces a new `TimeMeasureLogger` class for logging\nexecution time of various operations. It also refactors the existing\ndiagnostics handling in the `NsmDebugInfoObject` and related classes\nto utilize this new logging mechanism. The `NsmDeviceDiagnostics`\nclass has been removed as its functionality is now integrated into\n`NsmDebugInfoObject`.\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-16346\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "94ccc56d6b14925bc1723da47c2ccd0f8e7640ac", "tree": "130cae38abbdec7c4ac540721785d4fed2eb1d3c", "parents": [ "3dd3ebbb35aefa6ce495e3ebfd2cb56ec2219f25" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Thu Jul 10 08:32:42 2025 +0530" }, "committer": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Wed Jul 16 19:19:27 2025 +0530" }, "message": "Added UTs for get Port ECC Counterso\n\n```\nChanges:\n- Added UTs for decode/encode req/resp functions\n- port number size changed to 16 bits\n- get port ecc counters sensor enabled\n\nFixes JIRA https://jirasw.nvidia.com/browse/iDGXOPENBMC-15778\n```\n" }, { "commit": "3dd3ebbb35aefa6ce495e3ebfd2cb56ec2219f25", "tree": "30fa00afa5a56e589575fe934924ed18608b598d", "parents": [ "800622e1455161249c6ab188114dd3b7543c4401" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Tue May 20 15:26:25 2025 +0530" }, "committer": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Wed Jul 16 17:45:16 2025 +0530" }, "message": "Added shmem support for get port ecc counters\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "800622e1455161249c6ab188114dd3b7543c4401", "tree": "b42d0bdafb0e939c751a27af15990ebce9ccfc82", "parents": [ "ae779c5ce97867a30298f61174dea7d9020fd024" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Tue May 20 07:27:59 2025 +0530" }, "committer": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Wed Jul 16 17:45:06 2025 +0530" }, "message": "Added Get Port ECC Counters Sensor support\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "ae779c5ce97867a30298f61174dea7d9020fd024", "tree": "6d2dadd100198d804c8ad6e34cc1149f58fd353a", "parents": [ "e62e8c97d0f9f0a6771784497d036bad6c8778bd" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Mon May 19 21:52:39 2025 +0530" }, "committer": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Wed Jul 16 17:35:27 2025 +0530" }, "message": "Added mockupResponder support for Get Port ECC Counters\n\nFixes NVBug https://nvbugspro.nvidia.com/bug/5104921\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "e62e8c97d0f9f0a6771784497d036bad6c8778bd", "tree": "86186b7d670fa3e86fb62cc411a8791b6acc073d", "parents": [ "02dd908372bbdb8bb6832fd97c64afbe71c3bac2" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Mon May 19 21:51:08 2025 +0530" }, "committer": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Wed Jul 16 17:30:09 2025 +0530" }, "message": "Added encode/decode functions for Get Port ECC Counters\n\nFixes NVBug https://nvbugspro.nvidia.com/bug/5104921\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "02dd908372bbdb8bb6832fd97c64afbe71c3bac2", "tree": "e7a463d24534c27e071f1b663902c3f9f50763da", "parents": [ "9cb588fd7cb743249803259106bf9d137d151c18" ], "author": { "name": "Harsh Verma", "email": "harshv@nvidia.com", "time": "Wed Jul 16 04:32:24 2025 -0700" }, "committer": { "name": "Harsh Verma", "email": "harshv@nvidia.com", "time": "Wed Jul 16 04:32:24 2025 -0700" }, "message": "Added NSM Type 1 API getNetworkAddresses support\n\n\n```\nChanges include:\n\n1. getNetworkAddresses request msg encode and decode functions\n2. getNetworkAddresses aggregate response msg sample encode and decode functions\n3. nsm raw command support for getNetworkAddresses\n4. nsmMockupResponder support for mock aggregate response\n5. getNetworkAddresses aggregate sensor implementation\n6. Added new dbus paths and associations for port network identifiers : Ethernet MAC Address , Permanent MAC Address , Node GUID\n```\n\n\nAddressing comments for Get Port Network Addresses support\n\n```\nchanges:\n1. updated UTs, added new cases\n2. remove endian conversion for mac address (collection data type)\n3. updated network address object path associations , aligned with design doc\n```\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15794\n" }, { "commit": "9cb588fd7cb743249803259106bf9d137d151c18", "tree": "72a654c9a4f9557e4772789547f5a8709d880db2", "parents": [ "2777a0915c8b5b5016a1c621791a0e92a8974a2e" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Wed Jul 16 09:42:04 2025 +0530" }, "committer": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Wed Jul 16 09:42:15 2025 +0530" }, "message": "Fix UTs for Get Ethernet Port Counters Request\n\n```\nChanges :\n- Fixes UTs for encode/decodeEthPortTelemetryCounterReq to align with comments\n addressed in commit 2777a0915c8b5b5016a1c621791a0e92a8974a2e\n```\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "2777a0915c8b5b5016a1c621791a0e92a8974a2e", "tree": "ab72bb708e9791a8df42316c1bbaaaaf422ef866", "parents": [ "0fd18f8128d393c4349da681ec25c9d82ff67ca3" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Mon Jul 07 20:04:25 2025 +0530" }, "committer": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Tue Jul 15 17:09:28 2025 +0530" }, "message": "Addressing comments for Eth Port Counters Support\n\n```\nChanges :\n- Updated decode/encode resp functions to handle data of different types\n- Updated decode/encode req functions : change portNumber data size\n- added size checks to mockupResponder response creation\n```\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "0fd18f8128d393c4349da681ec25c9d82ff67ca3", "tree": "9c96d7c20fdb7a88917946c121cabf62e05c99ff", "parents": [ "a51088936046b3ae3ec89e84862f1798db7f0182" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Mon May 19 13:27:53 2025 +0530" }, "committer": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Tue Jul 15 17:09:28 2025 +0530" }, "message": "Addressing comments for Eth Port Counters aggregate sensor\n\n```\nChanges :\n- Added NSM_GET_ETH_PORT_TELEMETRY_COUNTER to supported commands in mockupResponder\n- Fixed EthPortTelemetryAggregator intialization\n- removed filler comments\n- Updated NSMPortMetrics implementation to align with new PDI\n- Updated NSM_GET_ETH_PORT_TELEMETRY_COUNTER command code\n```\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "a51088936046b3ae3ec89e84862f1798db7f0182", "tree": "28ad8e19b7b767c5c34fcc637a641a5b5dceea04", "parents": [ "fc058365135c06253163b1514cd4652b52f60561" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Thu Apr 03 14:34:15 2025 +0530" }, "committer": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Tue Jul 15 17:09:28 2025 +0530" }, "message": "Added Aggregate sensor for get ethernet port counters\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "fc058365135c06253163b1514cd4652b52f60561", "tree": "bb4348833d4bf357152c5835d4d6ef02241644fc", "parents": [ "1060d2a2282a3b39a390d86c6ce116ef35e3f1fe" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Mon Mar 10 14:53:17 2025 +0530" }, "committer": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Tue Jul 15 17:09:28 2025 +0530" }, "message": "Added MockupResponder for Ethernet Port Telemetry Counters\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "1060d2a2282a3b39a390d86c6ce116ef35e3f1fe", "tree": "6a117a84d1b56b80ff96a3565ceb451d45ac7b74", "parents": [ "ba56422284d6e5d0e7d6e0a31aeacb642dcd42b1" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Mon Mar 10 15:16:47 2025 +0530" }, "committer": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Tue Jul 15 17:09:28 2025 +0530" }, "message": "Added encode/decode functions for Ethernet Port Telemetry Counters\n\n Fixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15778\n" }, { "commit": "ba56422284d6e5d0e7d6e0a31aeacb642dcd42b1", "tree": "37cebb36db5e48384c7f4adebbf2a25296557ddb", "parents": [ "16cb64d4693cfcaced6227532af1307cac220d96" ], "author": { "name": "raghulr", "email": "raghulr@ami.com", "time": "Mon Jun 30 20:29:27 2025 +0530" }, "committer": { "name": "svcdgx", "email": "group_3005_bot_871b8a89a193009b5d6a6b2fa1d60393@noreply.gitlab-master.nvidia.com", "time": "Sat Jul 12 02:02:30 2025 -0700" }, "message": "Adding support to MCU reset boot reasons\n\nfixes jira https://jirasw.nvidia.com/browse/DGXOPENBMC-18081\n\nSome more new MCU reset/boot reason are added support on NSM spec.\nThis commit adding support to get all boot reason bit fields\n(256 bits) and decode that values to update it on dbus\nbootreason property.\n\nSigned-off-by: raghulr \u003craghulr@ami.com\u003e\n" }, { "commit": "16cb64d4693cfcaced6227532af1307cac220d96", "tree": "a2ab5197e970ea8dfd48fd04c1cbc7162d78a11e", "parents": [ "7ae9c137ef985d251bb0a8905eeb0c26cc667301" ], "author": { "name": "Karthick Sundarrajan", "email": "ksundarrajan@nvidia.com", "time": "Thu Jul 10 03:21:58 2025 -0700" }, "committer": { "name": "Karthick Sundarrajan", "email": "ksundarrajan@nvidia.com", "time": "Fri Jul 11 00:26:23 2025 -0700" }, "message": "Add support for type-2 PCIeDevice group0 telemetry\n\nAdded type-2 support for GROUP_ID_0 and GROUP_ID_1 to populate\nPCIeDevice telemetry.\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5306349\n\nTested:\n```\nroot@hgxb300:~# busctl introspect \"xyz.openbmc_project.NSM\" \"/xyz/openbmc_project/inventory/system/chassis/HGX_ConnectX_0/PCIeDevices/ConnectX_0\" --full\nNAME TYPE SIGNATURE RESULT/VALUE FLAGS\norg.freedesktop.DBus.Introspectable interface - - -\n.Introspect method - s -\norg.freedesktop.DBus.Peer interface - - -\n.GetMachineId method - s -\n.Ping method - - -\norg.freedesktop.DBus.Properties interface - - -\n.Get method ss v -\n.GetAll method s a{sv} -\n.Set method ssv - -\n.PropertiesChanged signal sa{sv}as - -\nxyz.openbmc_project.Association.Definitions interface - - -\n.Associations property a(sss) 1 \"chassis\" \"pciedevice\" \"/xyz/openbmc_project/inventory/system/chassis/HGX_ConnectX_0\" emits-change writable\nxyz.openbmc_project.Common.UUID interface - - -\n.UUID property s \"ae0a96c0-cb06-11e5-a837-3c6d669340f0\" emits-change writable\nxyz.openbmc_project.Inventory.Decorator.Asset interface - - -\n.BuildDate property s \"0000-00-00T00:00:00Z\" emits-change writable\n.Manufacturer property s \"NVIDIA\" emits-change writable\n.Model property s \"Nvidia ConnectX8 XDR IB/800GBE for Nvidia B300 NVL8 ------- System\" emits-change writable\n.Name property s \"NA\" emits-change writable\n.PartNumber property s \"MLX000647\" emits-change writable\n.SKU property s \"NA\" emits-change writable\n.SerialNumber property s \"1662425750916\" emits-change writable\n.SparePartNumber property s \"\" emits-change writable\n.SubModel property s \"\" emits-change writable\nxyz.openbmc_project.Inventory.Item.PCIeDevice interface - - -\n.DeviceType property s \"SingleFunction\" emits-change writable\n.Function0ClassCode property s \"0x000000\" emits-change writable\n.Function0DeviceClass property s \"ProcessingAccelerators\" emits-change writable\n.Function0DeviceId property s \"0x1023\" emits-change writable\n.Function0FunctionType property s \"Physical\" emits-change writable\n.Function0RevisionId property s \"0x00\" emits-change writable\n.Function0SubsystemId property s \"0x0101\" emits-change writable\n.Function0SubsystemVendorId property s \"0x15B3\" emits-change writable\n.Function0VendorId property s \"0x15B3\" emits-change writable\n.Function1ClassCode property s \"\" emits-change writable\n...\n...\n.Function7VendorId property s \"\" emits-change writable\n.GenerationInUse property s \"xyz.openbmc_project.Inventory.Item.PCIeSlot.Generations.Gen5\" emits-change writable\n.GenerationSupported property s \"xyz.openbmc_project.Inventory.Item.PCIeSlot.Generations.Unknown\" emits-change writable\n.LanesInUse property u 16 emits-change writable\n.MaxLanes property u 16 emits-change writable\n.MaxPCIeType property s \"xyz.openbmc_project.Inventory.Item.PCIeDevice.PCIeTypes.Gen5\" emits-change writable\n.PCIeType property s \"xyz.openbmc_project.Inventory.Item.PCIeDevice.PCIeTypes.Gen5\" emits-change writable\nxyz.openbmc_project.State.Decorator.Health interface - - -\n.Health property s \"xyz.openbmc_project.State.Decorator.Health.HealthType.OK\" emits-change writable\nroot@hgxb300:~# busctl introspect \"xyz.openbmc_project.NSM\" \"/xyz/openbmc_project/inventory/system/chassis/HGX_NVLinkManagementNIC_0/PCIeDevices/NVLinkManagementNIC_0\" --full\nNAME TYPE SIGNATURE RESULT/VALUE FLAGS\norg.freedesktop.DBus.Introspectable interface - - -\n.Introspect method - s -\norg.freedesktop.DBus.Peer interface - - -\n.GetMachineId method - s -\n.Ping method - - -\norg.freedesktop.DBus.Properties interface - - -\n.Get method ss v -\n.GetAll method s a{sv} -\n.Set method ssv - -\n.PropertiesChanged signal sa{sv}as - -\nxyz.openbmc_project.Association.Definitions interface - - -\n.Associations property a(sss) 1 \"chassis\" \"pciedevice\" \"/xyz/openbmc_project/inventory/system/chassis/HGX_NVLinkManagementNIC_0\" emits-change writable\nxyz.openbmc_project.Common.UUID interface - - -\n.UUID property s \"ae0a96c0-cb06-11e5-a837-3c6d669340ec\" emits-change writable\nxyz.openbmc_project.Inventory.Decorator.Asset interface - - -\n.BuildDate property s \"0000-00-00T00:00:00Z\" emits-change writable\n.Manufacturer property s \"NVIDIA\" emits-change writable\n.Model property s \"Nvidia ConnectX7 mezz for Nvidia B300 NVL8 --------System\" emits-change writable\n.Name property s \"NA\" emits-change writable\n.PartNumber property s \"V000S4N03X\" emits-change writable\n.SKU property s \"NA\" emits-change writable\n.SerialNumber property s \"1662425750916\" emits-change writable\n.SparePartNumber property s \"\" emits-change writable\n.SubModel property s \"\" emits-change writable\nxyz.openbmc_project.Inventory.Decorator.PCIeRefClock interface - - -\n.PCIeReferenceClockCount property t 0 emits-change\n.PCIeReferenceClockEnabled property b false emits-change\nxyz.openbmc_project.Inventory.Item.PCIeDevice interface - - -\n.DeviceType property s \"SingleFunction\" emits-change writable\n.Function0ClassCode property s \"0x000000\" emits-change writable\n.Function0DeviceClass property s \"ProcessingAccelerators\" emits-change writable\n.Function0DeviceId property s \"0x1021\" emits-change writable\n.Function0FunctionType property s \"Physical\" emits-change writable\n.Function0RevisionId property s \"0x00\" emits-change writable\n.Function0SubsystemId property s \"0x1113\" emits-change writable\n.Function0SubsystemVendorId property s \"0x15B3\" emits-change writable\n.Function0VendorId property s \"0x15B3\" emits-change writable\n.Function1ClassCode property s \"\" emits-change writable\n...\n...\n.Function7VendorId property s \"\" emits-change writable\n.GenerationInUse property s \"xyz.openbmc_project.Inventory.Item.PCIeSlot.Generations.Gen3\" emits-change writable\n.GenerationSupported property s \"xyz.openbmc_project.Inventory.Item.PCIeSlot.Generations.Unknown\" emits-change writable\n.LanesInUse property u 2 emits-change writable\n.MaxLanes property u 2 emits-change writable\n.MaxPCIeType property s \"xyz.openbmc_project.Inventory.Item.PCIeDevice.PCIeTypes.Gen4\" emits-change writable\n.PCIeType property s \"xyz.openbmc_project.Inventory.Item.PCIeDevice.PCIeTypes.Gen3\" emits-change writable\nxyz.openbmc_project.State.Chassis interface - - -\n.CurrentPowerState property s \"xyz.openbmc_project.State.Chassis.PowerState.On\" emits-change writable\n.CurrentPowerStatus property s \"xyz.openbmc_project.State.Chassis.PowerStatus.Undefined\" emits-change writable\n.LastStateChangeTime property t 0 emits-change writable\n.RequestedPowerTransition property s \"xyz.openbmc_project.State.Chassis.Transition.Off\" emits-change writable\nxyz.openbmc_project.State.Decorator.Health interface - - -\n.Health property s \"xyz.openbmc_project.State.Decorator.Health.HealthType.OK\" emits-change writable\nroot@hgxb300:~#\nroot@hgxb300:~# curl 192.168.31.1/redfish/v1/Chassis/HGX_ConnectX_0/PCIeDevices/ConnectX_0\n{\n \"@odata.id\": \"/redfish/v1/Chassis/HGX_ConnectX_0/PCIeDevices/ConnectX_0\",\n \"@odata.type\": \"#PCIeDevice.v1_14_0.PCIeDevice\",\n \"DeviceType\": \"SingleFunction\",\n \"Id\": \"ConnectX_0\",\n \"Links\": {\n \"Switch\": {\n \"@odata.id\": \"/redfish/v1/Fabrics/HGX_PCIeTopology_0/Switches/ConnectX_Switch_0\"\n }\n },\n \"Manufacturer\": \"NVIDIA\",\n \"Model\": \"Nvidia ConnectX8 XDR IB/800GBE for Nvidia B300 NVL8 ----- System\",\n \"Name\": \"PCIe Device\",\n \"Oem\": {\n \"Nvidia\": {\n \"@odata.type\": \"#NvidiaPCIeDevice.v1_2_0.NvidiaPCIeDevice\"\n }\n },\n \"PCIeFunctions\": {\n \"@odata.id\": \"/redfish/v1/Chassis/HGX_ConnectX_0/PCIeDevices/ConnectX_0/PCIeFunctions\"\n },\n \"PCIeInterface\": {\n \"LanesInUse\": 16,\n \"MaxLanes\": 16,\n \"MaxPCIeType\": \"Gen5\",\n \"PCIeType\": \"Gen5\"\n },\n \"PartNumber\": \"MLX000647\",\n \"SerialNumber\": \"1662425750916\",\n \"Status\": {\n \"Conditions\": [],\n \"Health\": \"OK\",\n \"HealthRollup\": \"OK\",\n \"State\": \"Enabled\"\n },\n \"UUID\": \"ae0a96c0-cb06-11e5-a837-3c6d669340f0\"\n}root@hgxb300:~#\nroot@hgxb300:~# curl 192.168.31.1/redfish/v1/Chassis/HGX_NVLinkManagementNIC_0/PCIeDevices/NVLinkManagementNIC_0\n{\n \"@odata.id\": \"/redfish/v1/Chassis/HGX_NVLinkManagementNIC_0/PCIeDevices/NVLinkManagementNIC_0\",\n \"@odata.type\": \"#PCIeDevice.v1_14_0.PCIeDevice\",\n \"DeviceType\": \"SingleFunction\",\n \"Id\": \"NVLinkManagementNIC_0\",\n \"Manufacturer\": \"NVIDIA\",\n \"Model\": \"Nvidia ConnectX7 mezz for Nvidia B300 NVL8 ---- System\",\n \"Name\": \"PCIe Device\",\n \"Oem\": {\n \"Nvidia\": {\n \"@odata.type\": \"#NvidiaPCIeDevice.v1_2_0.NvidiaPCIeDevice\",\n \"PCIeReferenceClockEnabled\": false\n }\n },\n \"PCIeFunctions\": {\n \"@odata.id\": \"/redfish/v1/Chassis/HGX_NVLinkManagementNIC_0/PCIeDevices/NVLinkManagementNIC_0/PCIeFunctions\"\n },\n \"PCIeInterface\": {\n \"LanesInUse\": 2,\n \"MaxLanes\": 2,\n \"MaxPCIeType\": \"Gen4\",\n \"PCIeType\": \"Gen3\"\n },\n \"PartNumber\": \"V000S4N03X\",\n \"SerialNumber\": \"1662425750916\",\n \"Status\": {\n \"Conditions\": [],\n \"Health\": \"OK\",\n \"HealthRollup\": \"OK\",\n \"State\": \"Enabled\"\n },\n \"UUID\": \"ae0a96c0-cb06-11e5-a837-3c6d669340ec\"\n}root@hgxb300:~#\n```\n```\n\nSigned-off-by: Karthick Sundarrajan \u003cksundarrajan@nvidia.com\u003e\n" }, { "commit": "80a277fea7b013130b75b598d0ecba86677c577d", "tree": "7a824cc2699bd71aab4018d8a0a9396c421cbc46", "parents": [ "d068b24413d056b5256c33d48de8461589b29432" ], "author": { "name": "Piotr Juda", "email": "pjuda@nvidia.com", "time": "Wed Jun 11 14:52:49 2025 +0000" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Add NSM_Chassis specialization for IRoTResponder class\n\nModifies NSM_IRoTResponder implementation to allow it to properly\nhandle interfaces and properties the NSMChassis class is responsible\nfor. This change allows adding the SPDMResponder interface after\nthe UUID value is set.\n\nIntroduces NSM_ChassisRoT configuration interface to allow using\nfirmware slots functionality without needing to use NSM_Chassis;\nthis can be combined with the NSM_ChassisIRoTResponder type.\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5321029\n\nSigned-off-by: Piotr Juda \u003cpjuda@nvidia.com\u003e\n" }, { "commit": "d068b24413d056b5256c33d48de8461589b29432", "tree": "cd3697506caa800f63a409dea6332e676e641d54", "parents": [ "19f86a89a5fa1eeb72b098a99d8dcc2d09729848" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Fri Jun 13 14:59:35 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Log improvement for tag mismatch\n\nFixes nvbug https://\n" }, { "commit": "19f86a89a5fa1eeb72b098a99d8dcc2d09729848", "tree": "21c35b029555b7c1cb48f1282faf29df4c5f375d", "parents": [ "3c52718573669f228e0c30a5f848ca617b8191ef" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Tue Jun 10 18:23:05 2025 +0200" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Fix incorrect timeout error message in NsmRawCommandHandler\n\nWhen a device issue causes a long-running command to timeout,\nthe wrong error message was being logged to the nsmd journal.\nThis commit updates the error message handling to correctly\nidentify and report timeout conditions in the\nNsmRawCommandHandler::doSendLongRunningRequest method.\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5238582\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "3c52718573669f228e0c30a5f848ca617b8191ef", "tree": "96585117a5491bc7167c0b0e62bdecff5a6cc679", "parents": [ "408f2a587424274e59eefffa63c8289b2f419a6f" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Fri Jun 06 12:48:54 2025 +0200" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Reverted sensor management by removing GPM sensors and updating logic\n\nThis commit removes the GPM sensors from the NsmDevice class and\nupdates the sensor polling logic to utilize round-robin sensors\ninstead. The changes streamline the sensor management process,\nensuring that the round-robin approach is consistently applied\nduring polling tasks.\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-17636\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "408f2a587424274e59eefffa63c8289b2f419a6f", "tree": "1d2df0f76d56061a13d88ffc2299b42b328502e2", "parents": [ "b19f9501154c15a5813213ab021e5a4e00d9dcb0" ], "author": { "name": "raghulr", "email": "raghulr@ami.com", "time": "Mon Jun 09 14:30:07 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Adding fixes to correctly update PRCKnob over DOE\n\nIssue:\n\nWhen try to configure PRC Knob setting over DOE\nit wrongly configure Host and DOE data.\n\nFix:\n\nThis issue is happen because of while configure\nover DOE previously configured host data fetch\nwrongly and ALLOW_HOST_ALLOW_DOE permission wrongly\nmapped. Now this commit adding the fixes.\n\nfixes nvbug https://nvbugspro.nvidia.com/bug/4952732\n\nSigned-off-by: raghulr \u003craghulr@ami.com\u003e\n" }, { "commit": "b19f9501154c15a5813213ab021e5a4e00d9dcb0", "tree": "f3f3b7e1adf4d7da08e78cf12ee93f22f063e1fe", "parents": [ "19592271baa862ec68b5682275f946951d6bcd5e" ], "author": { "name": "raghulr", "email": "raghulr@ami.com", "time": "Tue May 27 19:18:00 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Adding fixes ErrorInjection payload support V2 req\n\nThis commit adding fix to support error injection\npayloads to use V2 request data.Since NSM message\nfor Get/Set/Activate payload using V2 request format.\n\nfixes nvbug https://nvbugspro.nvidia.com/bug/5301740\n\nSigned-off-by: raghulr \u003craghulr@ami.com\u003e\n" }, { "commit": "19592271baa862ec68b5682275f946951d6bcd5e", "tree": "56cd21178377e061ff45633bb4a28d6071ac5da9", "parents": [ "bc0e4afbade40bf764804421e5157b34310a2e82" ], "author": { "name": "Ayush Kumar Thakur", "email": "ayushkumart@nvidia.com", "time": "Fri Jun 06 02:03:59 2025 -0700" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Remove mctp signal from queue in case of error in signal processing\n\n\u0027\u0027\u0027\nThe signal having error in processing was not removed from the queue.\nIn case of continuous error in processing mctp signal and b2b property change signal from mctp it can led to increase in size of the queue. This commit will help to fix the issue.\n\u0027\u0027\u0027\n\nFixes Jira https://\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n\n\n(cherry picked from commit bca18d084ed4b651c1ff878270ba10084d0d5830)\n\nCo-authored-by: Ayush Kumar Thakur \u003cayushkumart@nvidia.com\u003e" }, { "commit": "bc0e4afbade40bf764804421e5157b34310a2e82", "tree": "93defc9a19a74e74325c490f057ded5a880ba160", "parents": [ "bcc2d024b81b69f9a5bfb9a14648b0c6729f1f97" ], "author": { "name": "Paweł Iwaneczko", "email": "piwaneczko@nvidia.com", "time": "Thu Jun 05 15:43:36 2025 +0200" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Add conditional compilation for NVIDIA shared memory tests\n\nThis commit introduces conditional compilation for the\nNsmNumericSensorShmem test, allowing it to be included\nonly when NVIDIA_SHMEM is defined. This change enhances\nthe flexibility of the test suite by enabling or disabling\nspecific tests based on the build configuration.\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-17636\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "bcc2d024b81b69f9a5bfb9a14648b0c6729f1f97", "tree": "7dd143fbfc0319893635992d17bb5da62fbb9fd0", "parents": [ "6928af7965a0e7c35135bf2244614f00e5908d17" ], "author": { "name": "Chinmay Shripad Hegde", "email": "chinmays@nvidia.com", "time": "Wed Jun 04 12:04:44 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Type6: Skip unknown firmware tags instead of error\n\nModify the firmware header and slot information decoding functions to\nskip unsupported tags instead of treating them as errors.\n\nThis makes the firmware decoding more resilient to protocol\nextensions by allowing unknown tags to be skipped rather than causing\nthe entire decode operation to fail.\n\nTested:\n 1. Verify unknown tags are skipped with FW which has additional tags\n 2. Verify tags are parsed on FW without additional fields\n\nFixes nvbug https://nvbugs/5317772\n\nSigned-off-by: Chinmay Shripad Hegde \u003cchinmays@nvidia.com\u003e\n" }, { "commit": "6928af7965a0e7c35135bf2244614f00e5908d17", "tree": "7dd143fbfc0319893635992d17bb5da62fbb9fd0", "parents": [ "a932465473229495d1cff7fa732882d07def3587" ], "author": { "name": "Utkarsh", "email": "uyadav@nvidia.com", "time": "Tue May 27 21:23:26 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Correcting the request parameter for type-2 multi-pcie commands\n\nChanges:\n1. Correct the request parameter required for multi pcie port related\ncommands, it does not have device index as input parameter.\n2. Correct the encoding for port info, bit 7 is for port type not bit 0.\n3. Cosmetic change, multi pcie telemetry commands are v2 not v1.\n\nTested on HW:\n```\nroot@hgxb300:~# nsmtool telemetry QueryMultiportScalarGroupTelemetry -d 0 -m 54 -u 0 -i 0 -v -t 0 -g 1\nnsmtool: \u003c6\u003e EID: 36, TAG: 0b, Tx: 10 de 80 89 02 24 03 00 00 01\nSuccess in creating the socket : RC \u003d 5\nSuccess in connecting to socket : RC \u003d 0\nSuccess in sending message type as VDM to mctp demux daemon : RC \u003d 4\nnsmtool: \u003c6\u003e EID: 36, TAG: 03, Rx: 10 de 00 89 02 24 00 00 00 14 00 05 00 00 00 05 00 00 00 05 00 00 00 05 00 00 00 05 00 00 00\n{\n \"Completion Code\": 0,\n \"NegotiatedLinkSpeed\": 5,\n \"NegotiatedLinkWidth\": 5,\n \"maxLinkSpeed\": 5,\n \"maxLinkWidth\": 5\n}\nroot@hgxb300:~# nsmtool telemetry QueryMultiportScalarGroupTelemetry -d 0 -m 54 -u 0 -i 0 -v -t 1 -g 1\nnsmtool: \u003c6\u003e EID: 36, TAG: 0b, Tx: 10 de 80 89 02 24 03 80 00 01\nSuccess in creating the socket : RC \u003d 5\nSuccess in connecting to socket : RC \u003d 0\nSuccess in sending message type as VDM to mctp demux daemon : RC \u003d 4\nnsmtool: \u003c6\u003e EID: 36, TAG: 03, Rx: 10 de 00 89 02 24 00 00 00 14 00 06 00 00 00 05 00 00 00 06 00 00 00 06 00 00 00 05 00 00 00\n{\n \"Completion Code\": 0,\n \"NegotiatedLinkSpeed\": 6,\n \"NegotiatedLinkWidth\": 5,\n \"maxLinkSpeed\": 6,\n \"maxLinkWidth\": 5\n}\nroot@hgxb300:~# busctl introspect xyz.openbmc_project.NSM /xyz/openbmc_project/inventory/system/fabrics/HGX_PCIeTopology_0/Switches/ConnectX_Switch_0/Ports/UP_0\nNAME TYPE SIGNATURE RESULT/VALUE FLAGS\norg.freedesktop.DBus.Introspectable interface - - -\n.Introspect method - s -\norg.freedesktop.DBus.Peer interface - - -\n.GetMachineId method - s -\n.Ping method - - -\norg.freedesktop.DBus.Properties interface - - -\n.Get method ss v -\n.GetAll method s a{sv} -\n.Set method ssv - -\n.PropertiesChanged signal sa{sv}as - -\nxyz.openbmc_project.Association.Definitions interface - - -\n.Associations property a(sss) 1 \"parent_device\" \"all_states\" \"/xyz/... emits-change writable\nxyz.openbmc_project.Inventory.Decorator.PortInfo interface - - -\n.CurrentSpeed property d 32 emits-change writable\n.MaxSpeed property d 32 emits-change writable\n.Protocol property s \"xyz.openbmc_project.Inventory.Decora... emits-change writable\n.Type property s \"xyz.openbmc_project.Inventory.Decora... emits-change writable\nxyz.openbmc_project.Inventory.Decorator.PortWidth interface - - -\n.ActiveWidth property u 16 emits-change writable\n.Width property u 16 emits-change writable\nxyz.openbmc_project.Inventory.Item.Port interface - - -\n.PortNumber property u 0 emits-change\nxyz.openbmc_project.PCIe.PCIeECC interface - - -\n.L0ToRecoveryCount property d 4 emits-change writable\n.LanesInUse property u 4294967295 emits-change writable\n.MaxLanes property u 0 emits-change writable\n.NAKReceivedCount property d 0 emits-change writable\n.NAKSentCount property d 0 emits-change writable\n.PCIeType property s \"xyz.openbmc_project.PCIe.PCIeECC.PCI... emits-change writable\n.ReplayCount property d 0 emits-change writable\n.ReplayRolloverCount property d 0 emits-change writable\n.UnsupportedRequestCount property d 0 emits-change writable\n.ceCount property d 0 emits-change writable\n.feCount property d 0 emits-change writable\n.nonfeCount property d 0 emits-change writable\n.ueCount property u 0 emits-change writable\nxyz.openbmc_project.PCIe.PCIeTransactionCounter interface - - -\n.OutboundReadPktCount property t 0 emits-change writable\n.OutboundReadTransfer property t 0 emits-change writable\n.OutboundTLPCount property t 0 emits-change writable\n.OutboundTLPsTransfer property t 0 emits-change writable\n.OutboundWritePktCount property t 0 emits-change writable\n.OutboundWriteTransfer property t 0 emits-change writable\n.ReqDroppedCreditCompletion property t 0 emits-change writable\n.ReqDroppedNonPostCredit property t 0 emits-change writable\n.ReqDroppedTag property t 0 emits-change writable\nroot@hgxb300:~#\n\nroot@hgxb300:~# busctl introspect xyz.openbmc_project.NSM /xyz/openbmc_project/inventory/system/fabrics/HGX_PCIeTopology_0/Switches/ConnectX_Switch_0/Ports/DOWN_0\nNAME TYPE SIGNATURE RESULT/VALUE FLAGS\norg.freedesktop.DBus.Introspectable interface - - -\n.Introspect method - s -\norg.freedesktop.DBus.Peer interface - - -\n.GetMachineId method - s -\n.Ping method - - -\norg.freedesktop.DBus.Properties interface - - -\n.Get method ss v -\n.GetAll method s a{sv} -\n.Set method ssv - -\n.PropertiesChanged signal sa{sv}as - -\nxyz.openbmc_project.Association.Definitions interface - - -\n.Associations property a(sss) 1 \"parent_device\" \"all_states\" \"/xyz/... emits-change writable\nxyz.openbmc_project.Inventory.Decorator.PortInfo interface - - -\n.CurrentSpeed property d 64 emits-change writable\n.MaxSpeed property d 64 emits-change writable\n.Protocol property s \"xyz.openbmc_project.Inventory.Decora... emits-change writable\n.Type property s \"xyz.openbmc_project.Inventory.Decora... emits-change writable\nxyz.openbmc_project.Inventory.Decorator.PortWidth interface - - -\n.ActiveWidth property u 16 emits-change writable\n.Width property u 16 emits-change writable\nxyz.openbmc_project.Inventory.Item.Port interface - - -\n.PortNumber property u 0 emits-change\nxyz.openbmc_project.PCIe.LTSSMState interface - - -\n.LTSSMState property s \"xyz.openbmc_project.PCIe.LTSSMState.... emits-change\nxyz.openbmc_project.PCIe.PCIeECC interface - - -\n.L0ToRecoveryCount property d 5 emits-change writable\n.LanesInUse property u 4294967295 emits-change writable\n.MaxLanes property u 0 emits-change writable\n.NAKReceivedCount property d 0 emits-change writable\n.NAKSentCount property d 0 emits-change writable\n.PCIeType property s \"xyz.openbmc_project.PCIe.PCIeECC.PCI... emits-change writable\n.ReplayCount property d 0 emits-change writable\n.ReplayRolloverCount property d 0 emits-change writable\n.UnsupportedRequestCount property d 0 emits-change writable\n.ceCount property d 0 emits-change writable\n.feCount property d 0 emits-change writable\n.nonfeCount property d 0 emits-change writable\n.ueCount property u 0 emits-change writable\nxyz.openbmc_project.PCIe.PCIeTransactionCounter interface - - -\n.OutboundReadPktCount property t 0 emits-change writable\n.OutboundReadTransfer property t 0 emits-change writable\n.OutboundTLPCount property t 0 emits-change writable\n.OutboundTLPsTransfer property t 0 emits-change writable\n.OutboundWritePktCount property t 0 emits-change writable\n.OutboundWriteTransfer property t 0 emits-change writable\n.ReqDroppedCreditCompletion property t 0 emits-change writable\n.ReqDroppedNonPostCredit property t 0 emits-change writable\n.ReqDroppedTag property t 0 emits-change writable\nroot@hgxb300:~#\n\n```\n\nFixes NvBug https://nvbugspro.nvidia.com/bug/5301683\nSigned-off-by: Utkarsh Yadav \u003cuyadav@nvidia.com\u003e\n" }, { "commit": "a932465473229495d1cff7fa732882d07def3587", "tree": "26bd746ce139b304c753f99a1faaf744f6d6b024", "parents": [ "6e4146d023700e23e9b15f75b2fcc502d8fec661" ], "author": { "name": "Paweł Iwaneczko", "email": "pawel.iwaneczko@conclusive.pl", "time": "Fri May 23 13:20:11 2025 +0200" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Add GPM sensor polling configuration and refactor sensor management\n\nThis commit introduces a new configuration option for GPM sensor\npolling time and refactors the sensor management logic to support\ndifferent polling types. The `addSensor` method is updated to use\nan enum for polling types, enhancing clarity and maintainability.\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-17166\nSigned-off-by: Paweł Iwaneczko \u003cpiwaneczko@nvidia.com\u003e\n" }, { "commit": "6e4146d023700e23e9b15f75b2fcc502d8fec661", "tree": "4efebc44696859d352c189abb762e097e0bd5226", "parents": [ "71e0ef8fa9ffea3a4d9d6e89c21a7fc043a1e597" ], "author": { "name": "Ayush Kumar Thakur", "email": "ayushkumart@nvidia.com", "time": "Mon May 26 11:47:43 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Clang format fix\n\nFixes nvbug https://nvbugs/5208433\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n" }, { "commit": "71e0ef8fa9ffea3a4d9d6e89c21a7fc043a1e597", "tree": "a1d3f5958ec17aedd143d364e043ea01388be9c7", "parents": [ "7eba6e774910679df542425432440d660e95e64a" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Thu May 22 15:40:37 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Fix handling of insertion to EidTable\n\nIssue: Eid Table can grow(may have duplicate entries) in size\nover time in case of\n1. Device re-discovery(mctp toggling)\n2. NSM event that involves discovery logic to run again\n\nThis commit fixes issue by checking multipmap eidTable\nhas the tuple already if yes then skip populating it\n\nExpectation is after initial discovery the size of eidTable will\nbe equal to number of devices. Or in some cases when device supports\nmultiple medium types, it will be double the number of devices\n\nFixes nvbug https://nvbugs/5209306\n" }, { "commit": "7eba6e774910679df542425432440d660e95e64a", "tree": "c6412e3aef128652b8690e57b8ca39426807e26d", "parents": [ "6d0216ae9cfd7ff91a8dac9bb9b925e208d28426" ], "author": { "name": "Ayush Kumar Thakur", "email": "ayushkumart@nvidia.com", "time": "Tue May 20 18:54:25 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Add async sleep in sensor polling loop\n\n\u0027\u0027\u0027\nThis commit enforces mandatory sleep of 20ms on completion of every polling loop for each eid. It will ensure mandatory CPU yield between 2 consecutive polling cycle.\n\nChanges:\n1. Add async sleep of 20ms when loop has already crossed polling time.\n2. Add async sleep of 20ms when device goes offline to online, and then continue further polling.\n3. Async sleep for 20ms and break the loop when the sensor on fron doesn\u0027t require update.\n\n\u0027\u0027\u0027\n\nFixes nvbug https://nvbugs/5208433\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n" }, { "commit": "6d0216ae9cfd7ff91a8dac9bb9b925e208d28426", "tree": "eb71a2c921cb8094b849c9425f6645efc77c9086", "parents": [ "11bcea365a8e765200f078983000e8d1fa80715b" ], "author": { "name": "Ayush Kumar Thakur", "email": "ayushkumart@nvidia.com", "time": "Fri May 23 15:00:00 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Use copy by value in co-routine handler function\n\n\u0027\u0027\u0027\nChanges required to avoid corruption of variable in case caller function goes out of scope.\n\u0027\u0027\u0027\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5208433\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n" }, { "commit": "11bcea365a8e765200f078983000e8d1fa80715b", "tree": "ed7e2f16c855939f2cb4655de6443effad854442", "parents": [ "9d23edc31611a805dbbbd00f811ab98ef1ebee28" ], "author": { "name": "Ayush Kumar Thakur", "email": "ayushkumart@nvidia.com", "time": "Mon May 19 19:34:42 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Create Co-routine task for Rediscovery events\n\n\u0027\u0027\u0027\nThis change will enable nsmd service to create a single co-routine task for each eid instead of creating new co-routine task for every rediscovery event.\nIt will help nsmd service to avoid piling up co-routine in case of back to back rediscovery events.\n\u0027\u0027\u0027\n\nFixes Jira https://\nsigned-off-by \u003cayushkumart@nvidia.com\u003e\n" }, { "commit": "9d23edc31611a805dbbbd00f811ab98ef1ebee28", "tree": "dffde0c7a07feec57c9696d7d1da4f552f8e6ea0", "parents": [ "3e693abf14cbfadd6a0e42e3bf5e3797f9411bab" ], "author": { "name": "Ayush Kumar Thakur", "email": "ayushkumart@nvidia.com", "time": "Tue May 20 17:07:37 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Modify getEidFromUUID function for efficient execution\n\n\u0027\u0027\u0027\nThis commits changes the function to use std::string_view instead of std::string. This will help to avoid creating a temporary std::string object, memory allocation etc. It will help in efficient execution of function\n\u0027\u0027\u0027\n\nFixes nvbug https://nvbugs/5208433\nsigned-off-by: ayushkumart@nvidia.com\n" }, { "commit": "3e693abf14cbfadd6a0e42e3bf5e3797f9411bab", "tree": "228ee151255440c261c058101a9426b21010c3f2", "parents": [ "d767e5638d24d742a3366023164a24668de94624" ], "author": { "name": "Ayush Kumar Thakur", "email": "ayushkumart@nvidia.com", "time": "Fri May 09 14:18:16 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Async Handling optimization for mctp resdiscovery signal\n\n\u0027\u0027\u0027\nChanges:\n1. Create individual queue for each EID to handle mctp rediscovery signal\n2. Use batch sensor update for offline devices and sleep at the end of batch operation to yield CPU.\n3. Make setOnline operation async\n4. Add async sleep of 10ms after batch update to yield cpu.\n\n\u0027\u0027\u0027\n\nFixes nvbug https://nvbugs/5208433\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n" }, { "commit": "d767e5638d24d742a3366023164a24668de94624", "tree": "3f2677d8bfdc86dee9d2e2ceda05887de1860b3c", "parents": [ "49b54b778733525f7f0ac180bb0c7e13c22c20b0" ], "author": { "name": "Aishwary Joshi", "email": "aishwaryjoshi31@gmail.com", "time": "Tue Apr 29 20:41:15 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Make asyn mctp signal handling\n\nIssue 1: Potential dbus timeout while mctp offline handling\nis being done\n- MCTP offline signal handling was cpu intensive operation\nwhich gets triggered through property change signal\n- MCTP service sends burst of signals when device transtion\nfrom Enabled to Disabled state\n\nIssue 2: Unordered handling of MCTP signals\nBefore this change whenever MCTP Enabled signal is recived\nit started a co-routine in the match call back\nas it involved IO interacting with the device while Disabled\n signal didn\u0027t involve IO and completed as part of match\ncall back execution\n\nWhats the impact of above issues and when it is seen\n- Impact is unordered processing of signals, which can lead\nto incorrect device state\n- Typically happens when the volume of property change signal\nis high and signals are flckering in nature\n- When the volume of signals to process is high it can\nlead to service dbus timeouts as well\n\nThis commit do following\n- To address both issues, mctp signal queuing mechanism\nhas been implemented so that singal processing is in the\nsame order as signal arrival\n- Additionall to fix issue #1, this commit migrated mctp\noffline signal to a co-routine and yield some cpu cycles\nin cpu intensive operation(set offline)\n\nFixes nvbug https://nvbugs/5208433, https://nvbugs/5217118\n" }, { "commit": "49b54b778733525f7f0ac180bb0c7e13c22c20b0", "tree": "2b43d232c9327ac741491bf0ba54ea915f69072b", "parents": [ "0eb6f6c88e71c73e8fe94cfdf44ff09226ac7cbe" ], "author": { "name": "akurdunkar", "email": "akurdunkar@nvidia.com", "time": "Thu Apr 17 18:19:18 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Revert Priorities for all event sources.\n\nFixes JIRA https://\n\nSigned-off-by: akurdunkar \u003cakurdunkar@nvidia.com\u003e\n" }, { "commit": "0eb6f6c88e71c73e8fe94cfdf44ff09226ac7cbe", "tree": "21aaad2aa74a885ffd92b5bf5bb2acb0bd72fe49", "parents": [ "f909e23c5761f3487efe03b2c54e2d7945cc4510" ], "author": { "name": "Ayush Kumar Thakur", "email": "ayushkumart@nvidia.com", "time": "Mon May 12 11:57:43 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Changes to fix async POST/PATCH infra\n\n\u0027\u0027\u0027\nNSMD created async object in round robin manner on POST/PATCH request. There was no handshake between bmcweb and nsmd for these objectPaths getting reused. Sometime it was causing overriding of value while creating RF response.\n\nThis change will enable nsmd to create unique object path for each post/patch request and delete these object paths after 2 mins.\n\u0027\u0027\u0027\n\nFixes nvbug https://nvbugspro.nvidia.com/bug/5266003\nsigned-off-by: \u003cayushkumart@nvidia.com\u003e\n" }, { "commit": "f909e23c5761f3487efe03b2c54e2d7945cc4510", "tree": "94c7f671fc6572982d2294679f9cedca1b0a83d9", "parents": [ "cf31070f09600e9e05d779640fc868d9015285f0" ], "author": { "name": "HARSH VERMA", "email": "harshv@nvidia.com", "time": "Wed May 14 19:43:32 2025 +0530" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Added support for AssetTag and ServiceLabel for CX*\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-15790\n" }, { "commit": "cf31070f09600e9e05d779640fc868d9015285f0", "tree": "1eb1e655a61171bb36a3e5971bfa165b7f00ec2a", "parents": [ "0de792c3169c10fe3191e429017d8ed38c11cdb9" ], "author": { "name": "Piotr Juda", "email": "pjuda@nvidia.com", "time": "Thu May 15 11:07:56 2025 +0000" }, "committer": { "name": "Harshit Aghera", "email": "haghera@nvidia.com", "time": "Mon Jul 07 12:05:58 2025 +0530" }, "message": "Add IRoTResponder class\n\nAdds NsmIRoTResponder class responsible for creating IRoT SPDM\nresponder objects and populating the Decorator.Asset SerialNumber\nproperty using Type 4 device ID data\n\nFixes JIRA https://jirasw.nvidia.com/browse/DGXOPENBMC-16730\n\nSigned-off-by: Piotr Juda \u003cpjuda@nvidia.com\u003e\n" } ], "next": "0de792c3169c10fe3191e429017d8ed38c11cdb9" }