)]}'
{
  "commit": "a1d74f409fd56c0c8be091f764f317414df40aaf",
  "tree": "b5d54d4836c91ad7c44ec177c652864a49cc6b36",
  "parents": [
    "922cf29dd8045f7348ce0f20145f46e8235faf21"
  ],
  "author": {
    "name": "Marek Vasut",
    "email": "marek.vasut+renesas@mailbox.org",
    "time": "Tue Jun 16 05:36:05 2026 +0200"
  },
  "committer": {
    "name": "Heinrich Schuchardt",
    "email": "heinrich.schuchardt@canonical.com",
    "time": "Sun Jun 21 09:19:35 2026 +0200"
  },
  "message": "doc: board: renesas: Document Renesas RZ/N1D and RZ/N1S as arm\n\nThe RZ/N1D and RZ/N1S contain Cortex-A7 core, which is 32bit ARM core.\nDocument the SoC as 32bit ARM instead of aarch64.\n\nFixes: a5b9f959439b (\"doc: renesas: add Renesas board docs\")\nSigned-off-by: Marek Vasut \u003cmarek.vasut+renesas@mailbox.org\u003e\nReviewed-by: Heinrich Schuchardt \u003cheinrich.schuchardt@canonical.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "fedfeed42e3fe87deff44570aa2c6504aa29cc08",
      "old_mode": 33188,
      "old_path": "doc/board/renesas/renesas.rst",
      "new_id": "1c94456eaed95b41c1d426ab13b880f7ee2f007a",
      "new_mode": 33188,
      "new_path": "doc/board/renesas/renesas.rst"
    }
  ]
}