| { | |
| "Bus": "44", | |
| "Address": "0x59", | |
| "Source": "max34451_mb", | |
| "IncludeWarnings": true, | |
| "FaultLogConfig": { | |
| "Command": "0xdc", | |
| "Offset": "14" | |
| }, | |
| "EnableBits": { | |
| "ForceLog": "15", | |
| "ClearLog": ["9", "14"] | |
| }, | |
| "Registers": { | |
| "MfrNvLogConfigReg": "0xd8" | |
| }, | |
| "SequencerRegisters": [ | |
| { | |
| "PageToPowerRailMap": { | |
| "0": "P13V5_CPU_S0", | |
| "1": "P13V5_CPU_S1", | |
| "2": "P0_VDD_33_DUAL", | |
| "3": "P0_VDD_18_DUAL", | |
| "4": "P0_VDD_11_SUS", | |
| "6": "P1_VDD_33_DUAL", | |
| "7": "P1_VDD_18_DUAL", | |
| "8": "P1_VDD_11_SUS", | |
| "10": "P12V", | |
| "11": "P1V8_CPLD", | |
| "12": "P5V_STBY", | |
| "13": "P3V3_STBY" | |
| } | |
| } | |
| ], | |
| "RailPriority": [ | |
| "P12V", | |
| "P5V_STBY", | |
| "P3V3_STBY", | |
| "P1V8_CPLD", | |
| "P13V5_CPU_S0", | |
| "P0_VDD_33_DUAL", | |
| "P0_VDD_18_DUAL", | |
| "P13V5_CPU_S1", | |
| "P1_VDD_33_DUAL", | |
| "P1_VDD_18_DUAL", | |
| "P0_VDD_11_SUS", | |
| "P1_VDD_11_SUS" | |
| ] | |
| } |