| [ | |
| { | |
| "Bus": "46", | |
| "Address": "0x76", | |
| "Source": "CPLD-M", | |
| "SetCPLDFlag": true, | |
| "CPLDRegisters": [ | |
| { | |
| "Register": "0x24", | |
| "BitToPowerRailMap": { | |
| "0": "PWRGD_CPU1_CD", | |
| "1": "PWRGD_CPU1_AB", | |
| "2": "PWRGD_CPU0_KL", | |
| "3": "PWRGD_CPU0_IJ", | |
| "4": "PWRGD_CPU0_GH", | |
| "5": "PWRGD_CPU0_EF", | |
| "6": "PWRGD_CPU0_CD", | |
| "7": "PWRGD_CPU0_AB" | |
| }, | |
| "ReverseFlag": [] | |
| }, | |
| { | |
| "Register": "0x25", | |
| "BitToPowerRailMap": { | |
| "0": "P12V", | |
| "4": "PWRGD_CPU1_KL", | |
| "5": "PWRGD_CPU1_IJ", | |
| "6": "PWRGD_CPU1_GH", | |
| "7": "PWRGD_CPU1_EF" | |
| }, | |
| "ReverseFlag": [] | |
| }, | |
| { | |
| "Register": "0x26", | |
| "BitToPowerRailMap": { | |
| "0": "P12V_BMC_STDBY" | |
| }, | |
| "ReverseFlag": [] | |
| } | |
| ] | |
| } | |
| ] |