| // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ |
| /* |
| * Copyright 2023 Mobileye Vision Technologies Ltd. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/mips-gic.h> |
| |
| #include <dt-bindings/clock/mobileye,eyeq5-clk.h> |
| |
| / { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "img,i6500"; |
| reg = <0>; |
| clocks = <&olb EQ5C_CPU_CORE0>; |
| }; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| /* These reserved memory regions are also defined in bootmanager |
| * for configuring inbound translation for BARS, don't change |
| * these without syncing with bootmanager |
| */ |
| shmem0_reserved: shmem@804000000 { |
| reg = <0x8 0x04000000 0x0 0x1000000>; |
| }; |
| shmem1_reserved: shmem@805000000 { |
| reg = <0x8 0x05000000 0x0 0x1000000>; |
| }; |
| pci0_msi_reserved: pci0-msi@806000000 { |
| reg = <0x8 0x06000000 0x0 0x100000>; |
| }; |
| pci1_msi_reserved: pci1-msi@806100000 { |
| reg = <0x8 0x06100000 0x0 0x100000>; |
| }; |
| |
| mini_coredump0_reserved: mini-coredump0@806200000 { |
| reg = <0x8 0x06200000 0x0 0x100000>; |
| }; |
| mhm_reserved_0: the-mhm-reserved-0@0 { |
| reg = <0x8 0x00000000 0x0 0x0000800>; |
| }; |
| |
| nvram@461fe00 { |
| compatible = "mobileye,eyeq5-bootloader-config", "nvmem-rmem"; |
| reg = <0x0 0x0461fe00 0x0 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| no-map; |
| |
| nvmem-layout { |
| compatible = "fixed-layout"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| eth0_mac: mac@7c { |
| reg = <0x7c 0x6>; |
| }; |
| |
| eth1_mac: mac@82 { |
| reg = <0x82 0x6>; |
| }; |
| }; |
| }; |
| }; |
| |
| aliases { |
| serial0 = &uart0; |
| serial1 = &uart1; |
| serial2 = &uart2; |
| }; |
| |
| cpu_intc: interrupt-controller { |
| compatible = "mti,cpu-interrupt-controller"; |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| }; |
| |
| xtal: xtal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <30000000>; |
| }; |
| |
| pclk: pclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <250000000>; /* 250MHz */ |
| }; |
| |
| tsu_clk: tsu-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <125000000>; /* 125MHz */ |
| }; |
| |
| soc: soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| compatible = "simple-bus"; |
| |
| i2c0: i2c@300000 { |
| compatible = "mobileye,eyeq5-i2c", "arm,primecell"; |
| reg = <0 0x300000 0x0 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <400000>; /* Fast mode */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; |
| clock-names = "i2cclk", "apb_pclk"; |
| resets = <&olb 0 13>; |
| i2c-transfer-timeout-us = <10000>; |
| mobileye,olb = <&olb 0>; |
| }; |
| |
| i2c1: i2c@400000 { |
| compatible = "mobileye,eyeq5-i2c", "arm,primecell"; |
| reg = <0 0x400000 0x0 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <400000>; /* Fast mode */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; |
| clock-names = "i2cclk", "apb_pclk"; |
| resets = <&olb 0 14>; |
| i2c-transfer-timeout-us = <10000>; |
| mobileye,olb = <&olb 1>; |
| }; |
| |
| i2c2: i2c@500000 { |
| compatible = "mobileye,eyeq5-i2c", "arm,primecell"; |
| reg = <0 0x500000 0x0 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <400000>; /* Fast mode */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; |
| clock-names = "i2cclk", "apb_pclk"; |
| resets = <&olb 0 15>; |
| i2c-transfer-timeout-us = <10000>; |
| mobileye,olb = <&olb 2>; |
| }; |
| |
| i2c3: i2c@600000 { |
| compatible = "mobileye,eyeq5-i2c", "arm,primecell"; |
| reg = <0 0x600000 0x0 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <400000>; /* Fast mode */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; |
| clock-names = "i2cclk", "apb_pclk"; |
| resets = <&olb 0 16>; |
| i2c-transfer-timeout-us = <10000>; |
| mobileye,olb = <&olb 3>; |
| }; |
| |
| i2c4: i2c@700000 { |
| compatible = "mobileye,eyeq5-i2c", "arm,primecell"; |
| reg = <0 0x700000 0x0 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <400000>; /* Fast mode */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&olb 35>, <&olb EQ5C_PER_I2C>; |
| clock-names = "i2cclk", "apb_pclk"; |
| resets = <&olb 0 17>; |
| i2c-transfer-timeout-us = <10000>; |
| mobileye,olb = <&olb 4>; |
| }; |
| |
| uart0: serial@800000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0 0x800000 0x0 0x1000>; |
| reg-io-width = <4>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; |
| clock-names = "uartclk", "apb_pclk"; |
| resets = <&olb 0 10>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart0_pins>; |
| }; |
| |
| uart1: serial@900000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0 0x900000 0x0 0x1000>; |
| reg-io-width = <4>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; |
| clock-names = "uartclk", "apb_pclk"; |
| resets = <&olb 0 11>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart1_pins>; |
| }; |
| |
| uart2: serial@a00000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0 0xa00000 0x0 0x1000>; |
| reg-io-width = <4>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; |
| clock-names = "uartclk", "apb_pclk"; |
| resets = <&olb 0 12>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart2_pins>; |
| }; |
| |
| olb: system-controller@e00000 { |
| compatible = "mobileye,eyeq5-olb", "syscon"; |
| reg = <0 0xe00000 0x0 0x400>; |
| #reset-cells = <2>; |
| #clock-cells = <1>; |
| clocks = <&xtal>; |
| clock-names = "ref"; |
| }; |
| |
| gic: interrupt-controller@140000 { |
| compatible = "mti,gic"; |
| reg = <0x0 0x140000 0x0 0x20000>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| |
| /* |
| * Declare the interrupt-parent even though the mti,gic |
| * binding doesn't require it, such that the kernel can |
| * figure out that cpu_intc is the root interrupt |
| * controller & should be probed first. |
| */ |
| interrupt-parent = <&cpu_intc>; |
| |
| timer { |
| compatible = "mti,gic-timer"; |
| interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; |
| clocks = <&olb EQ5C_CPU_CORE0>; |
| }; |
| }; |
| |
| emmc: mmc@2200000 { |
| compatible = "mobileye,eyeq-sd4hc", "cdns,sd4hc"; |
| reg = <0 0x2200000 0x0 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&olb EQ5C_PER_EMMC>; |
| bus-width = <8>; |
| max-frequency = <200000000>; |
| mmc-ddr-1_8v; |
| sd-uhs-ddr50; |
| mmc-hs200-1_8v; |
| mmc-hs400-1_8v; |
| mmc-hs400-enhanced-strobe; |
| |
| cdns,phy-input-delay-legacy = <4>; |
| cdns,phy-input-delay-mmc-highspeed = <2>; |
| cdns,phy-input-delay-mmc-ddr = <3>; |
| cdns,phy-dll-delay-sdclk = <32>; |
| cdns,phy-dll-delay-sdclk-hsmmc = <32>; |
| cdns,phy-dll-delay-strobe = <32>; |
| }; |
| |
| gpio0: gpio@1400000 { |
| compatible = "mobileye,eyeq5-gpio"; |
| reg = <0x0 0x1400000 0x0 0x1000>; |
| gpio-bank = <0>; |
| ngpios = <29>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 14 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&olb 0 0 29>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| resets = <&olb 0 26>; |
| }; |
| |
| gpio1: gpio@1500000 { |
| compatible = "mobileye,eyeq5-gpio"; |
| reg = <0x0 0x1500000 0x0 0x1000>; |
| gpio-bank = <1>; |
| ngpios = <23>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 14 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&olb 0 29 23>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| resets = <&olb 0 26>; |
| }; |
| }; |
| }; |
| |
| #include "eyeq5-pins.dtsi" |
