drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_regs.c - linux - Git at Google

 // SPDX-License-Identifier: GPL-2.0+
 /* Microchip lan969x Switch driver
  *
  * Copyright (c) 2024 Microchip Technology Inc.
  */

 /* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200.
  * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b
  */

 #include "lan969x.h"

 const unsigned int lan969x_tsize[TSIZE_LAST] = {
 	[TC_DEV10G] = 10,
 	[TC_DEV2G5] = 28,
 	[TC_DEV5G] = 4,
 	[TC_PCS10G_BR] = 10,
 	[TC_PCS5G_BR] = 4,
 };

 const unsigned int lan969x_raddr[RADDR_LAST] = {
 	[RA_CPU_PROC_CTRL] = 160,
 	[RA_GCB_SOFT_RST] = 12,
 	[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20,
 };

 const unsigned int lan969x_rcnt[RCNT_LAST] = {
 	[RC_ANA_AC_OWN_UPSID] = 1,
 	[RC_ANA_ACL_VCAP_S2_CFG] = 35,
 	[RC_ANA_ACL_OWN_UPSID] = 1,
 	[RC_ANA_CL_OWN_UPSID] = 1,
 	[RC_ANA_L2_OWN_UPSID] = 1,
 	[RC_ASM_PORT_CFG] = 32,
 	[RC_DSM_BUF_CFG] = 32,
 	[RC_DSM_DEV_TX_STOP_WM_CFG] = 32,
 	[RC_DSM_RX_PAUSE_CFG] = 32,
 	[RC_DSM_MAC_CFG] = 32,
 	[RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30,
 	[RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30,
 	[RC_DSM_TAXI_CAL_CFG] = 6,
 	[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30,
 	[RC_HSCH_PORT_MODE] = 35,
 	[RC_QFWD_SWITCH_PORT_MODE] = 35,
 	[RC_QSYS_PAUSE_CFG] = 35,
 	[RC_QSYS_ATOP] = 35,
 	[RC_QSYS_FWD_PRESSURE] = 35,
 	[RC_QSYS_CAL_AUTO] = 4,
 	[RC_REW_OWN_UPSID] = 1,
 	[RC_REW_RTAG_ETAG_CTRL] = 35,
 };

 const unsigned int lan969x_gaddr[GADDR_LAST] = {
 	[GA_ANA_AC_RAM_CTRL] = 202000,
 	[GA_ANA_AC_PS_COMMON] = 202880,
 	[GA_ANA_AC_MIRROR_PROBE] = 203232,
 	[GA_ANA_AC_SRC] = 201728,
 	[GA_ANA_AC_PGID] = 131072,
 	[GA_ANA_AC_TSN_SF] = 202028,
 	[GA_ANA_AC_TSN_SF_CFG] = 148480,
 	[GA_ANA_AC_TSN_SF_STATUS] = 147936,
 	[GA_ANA_AC_SG_ACCESS] = 202032,
 	[GA_ANA_AC_SG_CONFIG] = 202752,
 	[GA_ANA_AC_SG_STATUS] = 147952,
 	[GA_ANA_AC_SG_STATUS_STICKY] = 202044,
 	[GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048,
 	[GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800,
 	[GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068,
 	[GA_ANA_ACL_COMMON] = 8192,
 	[GA_ANA_ACL_KEY_SEL] = 9204,
 	[GA_ANA_ACL_CNT_B] = 4096,
 	[GA_ANA_ACL_STICKY] = 10852,
 	[GA_ANA_AC_POL_POL_ALL_CFG] = 17504,
 	[GA_ANA_AC_POL_COMMON_BDLB] = 19464,
 	[GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472,
 	[GA_ANA_AC_SDLB_LBGRP_TBL] = 31788,
 	[GA_ANA_CL_PORT] = 65536,
 	[GA_ANA_CL_COMMON] = 87040,
 	[GA_ANA_L2_COMMON] = 561928,
 	[GA_ANA_L3_COMMON] = 370752,
 	[GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580,
 	[GA_ASM_CFG] = 18304,
 	[GA_ASM_PFC_TIMER_CFG] = 15568,
 	[GA_ASM_LBK_WM_CFG] = 15596,
 	[GA_ASM_LBK_MISC_CFG] = 15608,
 	[GA_ASM_RAM_CTRL] = 15684,
 	[GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864,
 	[GA_EACL_CNT_TBL] = 30720,
 	[GA_EACL_POL_CFG] = 38400,
 	[GA_EACL_ES2_STICKY] = 29072,
 	[GA_EACL_RAM_CTRL] = 29112,
 	[GA_GCB_SIO_CTRL] = 560,
 	[GA_HSCH_HSCH_DWRR] = 36480,
 	[GA_HSCH_HSCH_MISC] = 36608,
 	[GA_HSCH_HSCH_LEAK_LISTS] = 37256,
 	[GA_HSCH_SYSTEM] = 37384,
 	[GA_HSCH_MMGT] = 36260,
 	[GA_HSCH_TAS_CONFIG] = 37696,
 	[GA_PTP_PTP_CFG] = 512,
 	[GA_PTP_PTP_TOD_DOMAINS] = 528,
 	[GA_PTP_PHASE_DETECTOR_CTRL] = 628,
 	[GA_QSYS_CALCFG] = 2164,
 	[GA_QSYS_RAM_CTRL] = 2204,
 	[GA_REW_COMMON] = 98304,
 	[GA_REW_PORT] = 49152,
 	[GA_REW_VOE_PORT_LM_CNT] = 90112,
 	[GA_REW_RAM_CTRL] = 93992,
 	[GA_VOP_RAM_CTRL] = 16368,
 	[GA_XQS_SYSTEM] = 5744,
 	[GA_XQS_QLIMIT_SHR] = 6912,
 };

 const unsigned int lan969x_gcnt[GCNT_LAST] = {
 	[GC_ANA_AC_SRC] = 67,
 	[GC_ANA_AC_PGID] = 1054,
 	[GC_ANA_AC_TSN_SF_CFG] = 256,
 	[GC_ANA_AC_STAT_CNT_CFG_PORT] = 35,
 	[GC_ANA_ACL_KEY_SEL] = 99,
 	[GC_ANA_ACL_CNT_A] = 1024,
 	[GC_ANA_ACL_CNT_B] = 1024,
 	[GC_ANA_AC_SDLB_LBGRP_TBL] = 5,
 	[GC_ANA_AC_SDLB_LBSET_TBL] = 496,
 	[GC_ANA_CL_PORT] = 35,
 	[GC_ANA_L2_ISDX_LIMIT] = 256,
 	[GC_ANA_L2_ISDX] = 1024,
 	[GC_ANA_L3_VLAN] = 4608,
 	[GC_ASM_DEV_STATISTICS] = 30,
 	[GC_EACL_ES2_KEY_SELECT_PROFILE] = 68,
 	[GC_EACL_CNT_TBL] = 512,
 	[GC_GCB_SIO_CTRL] = 1,
 	[GC_HSCH_HSCH_CFG] = 1120,
 	[GC_HSCH_HSCH_DWRR] = 32,
 	[GC_PTP_PTP_PINS] = 8,
 	[GC_PTP_PHASE_DETECTOR_CTRL] = 8,
 	[GC_REW_PORT] = 35,
 	[GC_REW_VOE_PORT_LM_CNT] = 240,
 };

 const unsigned int lan969x_gsize[GSIZE_LAST] = {
 	[GW_ANA_AC_SRC] = 4,
 	[GW_ANA_L2_COMMON] = 712,
 	[GW_ASM_CFG] = 1092,
 	[GW_CPU_CPU_REGS] = 180,
 	[GW_DEV2G5_PHASE_DETECTOR_CTRL] = 12,
 	[GW_FDMA_FDMA] = 448,
 	[GW_GCB_CHIP_REGS] = 180,
 	[GW_HSCH_TAS_CONFIG] = 16,
 	[GW_PTP_PHASE_DETECTOR_CTRL] = 12,
 	[GW_QSYS_PAUSE_CFG] = 988,
 };

 const unsigned int lan969x_fpos[FPOS_LAST] = {
 	[FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 7,
 	[FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 6,
 	[FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 5,
 	[FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 4,
 	[FP_CPU_PROC_CTRL_VINITHI] = 3,
 	[FP_CPU_PROC_CTRL_CFGTE] = 2,
 	[FP_CPU_PROC_CTRL_CP15S_DISABLE] = 1,
 	[FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 0,
 	[FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 8,
 	[FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 5,
 	[FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 3,
 	[FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 5,
 	[FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 4,
 	[FP_FDMA_CH_CFG_CH_INJ_PORT] = 3,
 	[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 27,
 	[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 25,
 	[FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 24,
 	[FP_PTP_PHAD_CTRL_PHAD_ENA] = 5,
 	[FP_PTP_PHAD_CTRL_PHAD_FAILED] = 3,
 };

 const unsigned int lan969x_fsize[FSIZE_LAST] = {
 	[FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 30,
 	[FW_ANA_AC_SRC_CFG_PORT_MASK] = 30,
 	[FW_ANA_AC_PGID_CFG_PORT_MASK] = 30,
 	[FW_ANA_AC_TSN_SF_PORT_NUM] = 7,
 	[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 8,
 	[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 8,
 	[FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 8,
 	[FW_ANA_AC_PORT_SGE_CFG_MASK] = 17,
 	[FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 9,
 	[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 3,
 	[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 9,
 	[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 9,
 	[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 3,
 	[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 9,
 	[FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 30,
 	[FW_ANA_L2_DLB_CFG_DLB_IDX] = 9,
 	[FW_ANA_L2_TSN_CFG_TSN_SFID] = 8,
 	[FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 30,
 	[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 2,
 	[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 7,
 	[FW_HSCH_SE_CFG_SE_DWRR_CNT] = 5,
 	[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 14,
 	[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 6,
 	[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 11,
 	[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 14,
 	[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 6,
 	[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 14,
 	[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 13,
 	[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 8,
 	[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 13,
 	[FW_PTP_PTP_PIN_INTR_INTR_PTP] = 8,
 	[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 8,
 	[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 8,
 	[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 3,
 	[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 6,
 	[FW_QRES_RES_CFG_WM_HIGH] = 11,
 	[FW_QRES_RES_STAT_MAXUSE] = 19,
 	[FW_QRES_RES_STAT_CUR_INUSE] = 19,
 	[FW_QSYS_PAUSE_CFG_PAUSE_START] = 11,
 	[FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 11,
 	[FW_QSYS_ATOP_ATOP] = 11,
 	[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 11,
 	[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 6,
 	[FW_XQS_STAT_CFG_STAT_VIEW] = 10,
 	[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 14,
 	[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 14,
 	[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 14,
 	[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 14,
 };
	// SPDX-License-Identifier: GPL-2.0+
	/* Microchip lan969x Switch driver
	*
	* Copyright (c) 2024 Microchip Technology Inc.
	*/

	/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200.
	* Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b
	*/

	#include "lan969x.h"

	const unsigned int lan969x_tsize[TSIZE_LAST] = {
	[TC_DEV10G] = 10,
	[TC_DEV2G5] = 28,
	[TC_DEV5G] = 4,
	[TC_PCS10G_BR] = 10,
	[TC_PCS5G_BR] = 4,
	};

	const unsigned int lan969x_raddr[RADDR_LAST] = {
	[RA_CPU_PROC_CTRL] = 160,
	[RA_GCB_SOFT_RST] = 12,
	[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20,
	};

	const unsigned int lan969x_rcnt[RCNT_LAST] = {
	[RC_ANA_AC_OWN_UPSID] = 1,
	[RC_ANA_ACL_VCAP_S2_CFG] = 35,
	[RC_ANA_ACL_OWN_UPSID] = 1,
	[RC_ANA_CL_OWN_UPSID] = 1,
	[RC_ANA_L2_OWN_UPSID] = 1,
	[RC_ASM_PORT_CFG] = 32,
	[RC_DSM_BUF_CFG] = 32,
	[RC_DSM_DEV_TX_STOP_WM_CFG] = 32,
	[RC_DSM_RX_PAUSE_CFG] = 32,
	[RC_DSM_MAC_CFG] = 32,
	[RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30,
	[RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30,
	[RC_DSM_TAXI_CAL_CFG] = 6,
	[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30,
	[RC_HSCH_PORT_MODE] = 35,
	[RC_QFWD_SWITCH_PORT_MODE] = 35,
	[RC_QSYS_PAUSE_CFG] = 35,
	[RC_QSYS_ATOP] = 35,
	[RC_QSYS_FWD_PRESSURE] = 35,
	[RC_QSYS_CAL_AUTO] = 4,
	[RC_REW_OWN_UPSID] = 1,
	[RC_REW_RTAG_ETAG_CTRL] = 35,
	};

	const unsigned int lan969x_gaddr[GADDR_LAST] = {
	[GA_ANA_AC_RAM_CTRL] = 202000,
	[GA_ANA_AC_PS_COMMON] = 202880,
	[GA_ANA_AC_MIRROR_PROBE] = 203232,
	[GA_ANA_AC_SRC] = 201728,
	[GA_ANA_AC_PGID] = 131072,
	[GA_ANA_AC_TSN_SF] = 202028,
	[GA_ANA_AC_TSN_SF_CFG] = 148480,
	[GA_ANA_AC_TSN_SF_STATUS] = 147936,
	[GA_ANA_AC_SG_ACCESS] = 202032,
	[GA_ANA_AC_SG_CONFIG] = 202752,
	[GA_ANA_AC_SG_STATUS] = 147952,
	[GA_ANA_AC_SG_STATUS_STICKY] = 202044,
	[GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048,
	[GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800,
	[GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068,
	[GA_ANA_ACL_COMMON] = 8192,
	[GA_ANA_ACL_KEY_SEL] = 9204,
	[GA_ANA_ACL_CNT_B] = 4096,
	[GA_ANA_ACL_STICKY] = 10852,
	[GA_ANA_AC_POL_POL_ALL_CFG] = 17504,
	[GA_ANA_AC_POL_COMMON_BDLB] = 19464,
	[GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472,
	[GA_ANA_AC_SDLB_LBGRP_TBL] = 31788,
	[GA_ANA_CL_PORT] = 65536,
	[GA_ANA_CL_COMMON] = 87040,
	[GA_ANA_L2_COMMON] = 561928,
	[GA_ANA_L3_COMMON] = 370752,
	[GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580,
	[GA_ASM_CFG] = 18304,
	[GA_ASM_PFC_TIMER_CFG] = 15568,
	[GA_ASM_LBK_WM_CFG] = 15596,
	[GA_ASM_LBK_MISC_CFG] = 15608,
	[GA_ASM_RAM_CTRL] = 15684,
	[GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864,
	[GA_EACL_CNT_TBL] = 30720,
	[GA_EACL_POL_CFG] = 38400,
	[GA_EACL_ES2_STICKY] = 29072,
	[GA_EACL_RAM_CTRL] = 29112,
	[GA_GCB_SIO_CTRL] = 560,
	[GA_HSCH_HSCH_DWRR] = 36480,
	[GA_HSCH_HSCH_MISC] = 36608,
	[GA_HSCH_HSCH_LEAK_LISTS] = 37256,
	[GA_HSCH_SYSTEM] = 37384,
	[GA_HSCH_MMGT] = 36260,
	[GA_HSCH_TAS_CONFIG] = 37696,
	[GA_PTP_PTP_CFG] = 512,
	[GA_PTP_PTP_TOD_DOMAINS] = 528,
	[GA_PTP_PHASE_DETECTOR_CTRL] = 628,
	[GA_QSYS_CALCFG] = 2164,
	[GA_QSYS_RAM_CTRL] = 2204,
	[GA_REW_COMMON] = 98304,
	[GA_REW_PORT] = 49152,
	[GA_REW_VOE_PORT_LM_CNT] = 90112,
	[GA_REW_RAM_CTRL] = 93992,
	[GA_VOP_RAM_CTRL] = 16368,
	[GA_XQS_SYSTEM] = 5744,
	[GA_XQS_QLIMIT_SHR] = 6912,
	};

	const unsigned int lan969x_gcnt[GCNT_LAST] = {
	[GC_ANA_AC_SRC] = 67,
	[GC_ANA_AC_PGID] = 1054,
	[GC_ANA_AC_TSN_SF_CFG] = 256,
	[GC_ANA_AC_STAT_CNT_CFG_PORT] = 35,
	[GC_ANA_ACL_KEY_SEL] = 99,
	[GC_ANA_ACL_CNT_A] = 1024,
	[GC_ANA_ACL_CNT_B] = 1024,
	[GC_ANA_AC_SDLB_LBGRP_TBL] = 5,
	[GC_ANA_AC_SDLB_LBSET_TBL] = 496,
	[GC_ANA_CL_PORT] = 35,
	[GC_ANA_L2_ISDX_LIMIT] = 256,
	[GC_ANA_L2_ISDX] = 1024,
	[GC_ANA_L3_VLAN] = 4608,
	[GC_ASM_DEV_STATISTICS] = 30,
	[GC_EACL_ES2_KEY_SELECT_PROFILE] = 68,
	[GC_EACL_CNT_TBL] = 512,
	[GC_GCB_SIO_CTRL] = 1,
	[GC_HSCH_HSCH_CFG] = 1120,
	[GC_HSCH_HSCH_DWRR] = 32,
	[GC_PTP_PTP_PINS] = 8,
	[GC_PTP_PHASE_DETECTOR_CTRL] = 8,
	[GC_REW_PORT] = 35,
	[GC_REW_VOE_PORT_LM_CNT] = 240,
	};

	const unsigned int lan969x_gsize[GSIZE_LAST] = {
	[GW_ANA_AC_SRC] = 4,
	[GW_ANA_L2_COMMON] = 712,
	[GW_ASM_CFG] = 1092,
	[GW_CPU_CPU_REGS] = 180,
	[GW_DEV2G5_PHASE_DETECTOR_CTRL] = 12,
	[GW_FDMA_FDMA] = 448,
	[GW_GCB_CHIP_REGS] = 180,
	[GW_HSCH_TAS_CONFIG] = 16,
	[GW_PTP_PHASE_DETECTOR_CTRL] = 12,
	[GW_QSYS_PAUSE_CFG] = 988,
	};

	const unsigned int lan969x_fpos[FPOS_LAST] = {
	[FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 7,
	[FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 6,
	[FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 5,
	[FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 4,
	[FP_CPU_PROC_CTRL_VINITHI] = 3,
	[FP_CPU_PROC_CTRL_CFGTE] = 2,
	[FP_CPU_PROC_CTRL_CP15S_DISABLE] = 1,
	[FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 0,
	[FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 8,
	[FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 5,
	[FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 3,
	[FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 5,
	[FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 4,
	[FP_FDMA_CH_CFG_CH_INJ_PORT] = 3,
	[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 27,
	[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 25,
	[FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 24,
	[FP_PTP_PHAD_CTRL_PHAD_ENA] = 5,
	[FP_PTP_PHAD_CTRL_PHAD_FAILED] = 3,
	};

	const unsigned int lan969x_fsize[FSIZE_LAST] = {
	[FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 30,
	[FW_ANA_AC_SRC_CFG_PORT_MASK] = 30,
	[FW_ANA_AC_PGID_CFG_PORT_MASK] = 30,
	[FW_ANA_AC_TSN_SF_PORT_NUM] = 7,
	[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 8,
	[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 8,
	[FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 8,
	[FW_ANA_AC_PORT_SGE_CFG_MASK] = 17,
	[FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 9,
	[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 3,
	[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 9,
	[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 9,
	[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 3,
	[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 9,
	[FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 30,
	[FW_ANA_L2_DLB_CFG_DLB_IDX] = 9,
	[FW_ANA_L2_TSN_CFG_TSN_SFID] = 8,
	[FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 30,
	[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 2,
	[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 7,
	[FW_HSCH_SE_CFG_SE_DWRR_CNT] = 5,
	[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 14,
	[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 6,
	[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 11,
	[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 14,
	[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 6,
	[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 14,
	[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 13,
	[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 8,
	[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 13,
	[FW_PTP_PTP_PIN_INTR_INTR_PTP] = 8,
	[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 8,
	[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 8,
	[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 3,
	[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 6,
	[FW_QRES_RES_CFG_WM_HIGH] = 11,
	[FW_QRES_RES_STAT_MAXUSE] = 19,
	[FW_QRES_RES_STAT_CUR_INUSE] = 19,
	[FW_QSYS_PAUSE_CFG_PAUSE_START] = 11,
	[FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 11,
	[FW_QSYS_ATOP_ATOP] = 11,
	[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 11,
	[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 6,
	[FW_XQS_STAT_CFG_STAT_VIEW] = 10,
	[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 14,
	[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 14,
	[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 14,
	[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 14,
	};