| // SPDX-License-Identifier: GPL-2.0 |
| /dts-v1/; |
| |
| #include <dt-bindings/interconnect/qcom,msm8974.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/qcom,gcc-msm8974.h> |
| #include <dt-bindings/clock/qcom,mmcc-msm8974.h> |
| #include <dt-bindings/clock/qcom,rpmcc.h> |
| #include <dt-bindings/reset/qcom,gcc-msm8974.h> |
| #include <dt-bindings/gpio/gpio.h> |
| |
| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| interrupt-parent = <&intc>; |
| |
| chosen { }; |
| |
| clocks { |
| xo_board: xo_board { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <19200000>; |
| }; |
| |
| sleep_clk: sleep_clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| |
| CPU0: cpu@0 { |
| compatible = "qcom,krait"; |
| enable-method = "qcom,kpss-acc-v2"; |
| device_type = "cpu"; |
| reg = <0>; |
| next-level-cache = <&L2>; |
| qcom,acc = <&acc0>; |
| qcom,saw = <&saw0>; |
| cpu-idle-states = <&CPU_SPC>; |
| }; |
| |
| CPU1: cpu@1 { |
| compatible = "qcom,krait"; |
| enable-method = "qcom,kpss-acc-v2"; |
| device_type = "cpu"; |
| reg = <1>; |
| next-level-cache = <&L2>; |
| qcom,acc = <&acc1>; |
| qcom,saw = <&saw1>; |
| cpu-idle-states = <&CPU_SPC>; |
| }; |
| |
| CPU2: cpu@2 { |
| compatible = "qcom,krait"; |
| enable-method = "qcom,kpss-acc-v2"; |
| device_type = "cpu"; |
| reg = <2>; |
| next-level-cache = <&L2>; |
| qcom,acc = <&acc2>; |
| qcom,saw = <&saw2>; |
| cpu-idle-states = <&CPU_SPC>; |
| }; |
| |
| CPU3: cpu@3 { |
| compatible = "qcom,krait"; |
| enable-method = "qcom,kpss-acc-v2"; |
| device_type = "cpu"; |
| reg = <3>; |
| next-level-cache = <&L2>; |
| qcom,acc = <&acc3>; |
| qcom,saw = <&saw3>; |
| cpu-idle-states = <&CPU_SPC>; |
| }; |
| |
| L2: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| qcom,saw = <&saw_l2>; |
| }; |
| |
| idle-states { |
| CPU_SPC: cpu-spc { |
| compatible = "qcom,idle-state-spc", |
| "arm,idle-state"; |
| entry-latency-us = <150>; |
| exit-latency-us = <200>; |
| min-residency-us = <2000>; |
| }; |
| }; |
| }; |
| |
| firmware { |
| scm { |
| compatible = "qcom,scm-msm8974", "qcom,scm"; |
| clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; |
| clock-names = "core", "bus", "iface"; |
| }; |
| }; |
| |
| memory@0 { |
| device_type = "memory"; |
| reg = <0x0 0x0>; |
| }; |
| |
| pmu { |
| compatible = "qcom,krait-pmu"; |
| interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| rpm: remoteproc { |
| compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc"; |
| |
| master-stats { |
| compatible = "qcom,rpm-master-stats"; |
| qcom,rpm-msg-ram = <&apss_master_stats>, |
| <&mpss_master_stats>, |
| <&lpss_master_stats>, |
| <&pronto_master_stats>; |
| qcom,master-names = "APSS", |
| "MPSS", |
| "LPSS", |
| "PRONTO"; |
| }; |
| |
| smd-edge { |
| interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&apcs 0>; |
| qcom,smd-edge = <15>; |
| |
| rpm_requests: rpm-requests { |
| compatible = "qcom,rpm-msm8974", "qcom,smd-rpm"; |
| qcom,smd-channels = "rpm_requests"; |
| |
| rpmcc: clock-controller { |
| compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; |
| #clock-cells = <1>; |
| clocks = <&xo_board>; |
| clock-names = "xo"; |
| }; |
| }; |
| }; |
| }; |
| |
| reserved_memory: reserved-memory { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| mpss_region: mpss@8000000 { |
| reg = <0x08000000 0x5100000>; |
| no-map; |
| }; |
| |
| mba_region: mba@d100000 { |
| reg = <0x0d100000 0x100000>; |
| no-map; |
| }; |
| |
| wcnss_region: wcnss@d200000 { |
| reg = <0x0d200000 0xa00000>; |
| no-map; |
| }; |
| |
| adsp_region: adsp@dc00000 { |
| reg = <0x0dc00000 0x1900000>; |
| no-map; |
| }; |
| |
| venus_region: memory@f500000 { |
| reg = <0x0f500000 0x500000>; |
| no-map; |
| }; |
| |
| smem_region: smem@fa00000 { |
| reg = <0xfa00000 0x200000>; |
| no-map; |
| }; |
| |
| tz_region: memory@fc00000 { |
| reg = <0x0fc00000 0x160000>; |
| no-map; |
| }; |
| |
| rfsa_mem: memory@fd60000 { |
| reg = <0x0fd60000 0x20000>; |
| no-map; |
| }; |
| |
| rmtfs@fd80000 { |
| compatible = "qcom,rmtfs-mem"; |
| reg = <0x0fd80000 0x180000>; |
| no-map; |
| |
| qcom,client-id = <1>; |
| }; |
| }; |
| |
| smem { |
| compatible = "qcom,smem"; |
| |
| memory-region = <&smem_region>; |
| qcom,rpm-msg-ram = <&rpm_msg_ram>; |
| |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| |
| smp2p-adsp { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <443>, <429>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; |
| |
| mboxes = <&apcs 10>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <2>; |
| |
| adsp_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| adsp_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-modem { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <435>, <428>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; |
| |
| mboxes = <&apcs 14>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <1>; |
| |
| modem_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| modem_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-wcnss { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <451>, <431>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; |
| |
| mboxes = <&apcs 18>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <4>; |
| |
| wcnss_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| wcnss_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smsm { |
| compatible = "qcom,smsm"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; |
| |
| apps_smsm: apps@0 { |
| reg = <0>; |
| |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| modem_smsm: modem@1 { |
| reg = <1>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| adsp_smsm: adsp@2 { |
| reg = <2>; |
| interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| wcnss_smsm: wcnss@7 { |
| reg = <7>; |
| interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| soc: soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "simple-bus"; |
| |
| intc: interrupt-controller@f9000000 { |
| compatible = "qcom,msm-qgic2"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0xf9000000 0x1000>, |
| <0xf9002000 0x1000>; |
| }; |
| |
| apcs: mailbox@f9011000 { |
| compatible = "qcom,msm8974-apcs-kpss-global", |
| "qcom,msm8994-apcs-kpss-global", "syscon"; |
| reg = <0xf9011000 0x1000>; |
| #mbox-cells = <1>; |
| }; |
| |
| saw_l2: power-manager@f9012000 { |
| compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2"; |
| reg = <0xf9012000 0x1000>; |
| }; |
| |
| watchdog@f9017000 { |
| compatible = "qcom,apss-wdt-msm8974", "qcom,kpss-wdt"; |
| reg = <0xf9017000 0x1000>; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&sleep_clk>; |
| }; |
| |
| timer@f9020000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0xf9020000 0x1000>; |
| clock-frequency = <19200000>; |
| |
| frame@f9021000 { |
| frame-number = <0>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0xf9021000 0x1000>, |
| <0xf9022000 0x1000>; |
| }; |
| |
| frame@f9023000 { |
| frame-number = <1>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0xf9023000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@f9024000 { |
| frame-number = <2>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0xf9024000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@f9025000 { |
| frame-number = <3>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0xf9025000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@f9026000 { |
| frame-number = <4>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0xf9026000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@f9027000 { |
| frame-number = <5>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0xf9027000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@f9028000 { |
| frame-number = <6>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0xf9028000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| acc0: power-manager@f9088000 { |
| compatible = "qcom,kpss-acc-v2"; |
| reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; |
| }; |
| |
| saw0: power-manager@f9089000 { |
| compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; |
| reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; |
| }; |
| |
| acc1: power-manager@f9098000 { |
| compatible = "qcom,kpss-acc-v2"; |
| reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; |
| }; |
| |
| saw1: power-manager@f9099000 { |
| compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; |
| reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; |
| }; |
| |
| acc2: power-manager@f90a8000 { |
| compatible = "qcom,kpss-acc-v2"; |
| reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; |
| }; |
| |
| saw2: power-manager@f90a9000 { |
| compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; |
| reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; |
| }; |
| |
| acc3: power-manager@f90b8000 { |
| compatible = "qcom,kpss-acc-v2"; |
| reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; |
| }; |
| |
| saw3: power-manager@f90b9000 { |
| compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; |
| reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; |
| }; |
| |
| sdhc_1: mmc@f9824900 { |
| compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; |
| reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; |
| reg-names = "hc", "core"; |
| interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| clocks = <&gcc GCC_SDCC1_AHB_CLK>, |
| <&gcc GCC_SDCC1_APPS_CLK>, |
| <&xo_board>; |
| clock-names = "iface", "core", "xo"; |
| bus-width = <8>; |
| non-removable; |
| |
| status = "disabled"; |
| }; |
| |
| sdhc_3: mmc@f9864900 { |
| compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; |
| reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; |
| reg-names = "hc", "core"; |
| interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| clocks = <&gcc GCC_SDCC3_AHB_CLK>, |
| <&gcc GCC_SDCC3_APPS_CLK>, |
| <&xo_board>; |
| clock-names = "iface", "core", "xo"; |
| bus-width = <4>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| sdhc_2: mmc@f98a4900 { |
| compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; |
| reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; |
| reg-names = "hc", "core"; |
| interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| clocks = <&gcc GCC_SDCC2_AHB_CLK>, |
| <&gcc GCC_SDCC2_APPS_CLK>, |
| <&xo_board>; |
| clock-names = "iface", "core", "xo"; |
| bus-width = <4>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| blsp1_uart1: serial@f991d000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0xf991d000 0x1000>; |
| interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| blsp1_uart2: serial@f991e000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0xf991e000 0x1000>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&blsp1_uart2_default>; |
| status = "disabled"; |
| }; |
| |
| blsp1_i2c1: i2c@f9923000 { |
| status = "disabled"; |
| compatible = "qcom,i2c-qup-v2.1.1"; |
| reg = <0xf9923000 0x1000>; |
| interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp1_i2c1_default>; |
| pinctrl-1 = <&blsp1_i2c1_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| blsp1_i2c2: i2c@f9924000 { |
| status = "disabled"; |
| compatible = "qcom,i2c-qup-v2.1.1"; |
| reg = <0xf9924000 0x1000>; |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp1_i2c2_default>; |
| pinctrl-1 = <&blsp1_i2c2_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| blsp1_i2c3: i2c@f9925000 { |
| status = "disabled"; |
| compatible = "qcom,i2c-qup-v2.1.1"; |
| reg = <0xf9925000 0x1000>; |
| interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp1_i2c3_default>; |
| pinctrl-1 = <&blsp1_i2c3_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| blsp1_i2c6: i2c@f9928000 { |
| status = "disabled"; |
| compatible = "qcom,i2c-qup-v2.1.1"; |
| reg = <0xf9928000 0x1000>; |
| interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp1_i2c6_default>; |
| pinctrl-1 = <&blsp1_i2c6_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| blsp2_dma: dma-controller@f9944000 { |
| compatible = "qcom,bam-v1.4.0"; |
| reg = <0xf9944000 0x19000>; |
| interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "bam_clk"; |
| #dma-cells = <1>; |
| qcom,ee = <0>; |
| }; |
| |
| blsp2_uart1: serial@f995d000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0xf995d000 0x1000>; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp2_uart1_default>; |
| pinctrl-1 = <&blsp2_uart1_sleep>; |
| status = "disabled"; |
| }; |
| |
| blsp2_uart2: serial@f995e000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0xf995e000 0x1000>; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| blsp2_uart4: serial@f9960000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0xf9960000 0x1000>; |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&blsp2_uart4_default>; |
| status = "disabled"; |
| }; |
| |
| blsp2_i2c2: i2c@f9964000 { |
| status = "disabled"; |
| compatible = "qcom,i2c-qup-v2.1.1"; |
| reg = <0xf9964000 0x1000>; |
| interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp2_i2c2_default>; |
| pinctrl-1 = <&blsp2_i2c2_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| blsp2_i2c5: i2c@f9967000 { |
| status = "disabled"; |
| compatible = "qcom,i2c-qup-v2.1.1"; |
| reg = <0xf9967000 0x1000>; |
| interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp2_i2c5_default>; |
| pinctrl-1 = <&blsp2_i2c5_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| blsp2_i2c6: i2c@f9968000 { |
| status = "disabled"; |
| compatible = "qcom,i2c-qup-v2.1.1"; |
| reg = <0xf9968000 0x1000>; |
| interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp2_i2c6_default>; |
| pinctrl-1 = <&blsp2_i2c6_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| usb: usb@f9a55000 { |
| compatible = "qcom,ci-hdrc"; |
| reg = <0xf9a55000 0x200>, |
| <0xf9a55200 0x200>; |
| interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_USB_HS_AHB_CLK>, |
| <&gcc GCC_USB_HS_SYSTEM_CLK>; |
| clock-names = "iface", "core"; |
| assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; |
| assigned-clock-rates = <75000000>; |
| resets = <&gcc GCC_USB_HS_BCR>; |
| reset-names = "core"; |
| phy_type = "ulpi"; |
| dr_mode = "otg"; |
| ahb-burst-config = <0>; |
| phy-names = "usb-phy"; |
| status = "disabled"; |
| #reset-cells = <1>; |
| |
| ulpi { |
| usb_hs1_phy: phy-0 { |
| compatible = "qcom,usb-hs-phy-msm8974", |
| "qcom,usb-hs-phy"; |
| #phy-cells = <0>; |
| clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; |
| clock-names = "ref", "sleep"; |
| resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; |
| reset-names = "phy", "por"; |
| status = "disabled"; |
| }; |
| |
| usb_hs2_phy: phy-1 { |
| compatible = "qcom,usb-hs-phy-msm8974", |
| "qcom,usb-hs-phy"; |
| #phy-cells = <0>; |
| clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; |
| clock-names = "ref", "sleep"; |
| resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>; |
| reset-names = "phy", "por"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| rng@f9bff000 { |
| compatible = "qcom,prng"; |
| reg = <0xf9bff000 0x200>; |
| clocks = <&gcc GCC_PRNG_AHB_CLK>; |
| clock-names = "core"; |
| }; |
| |
| pronto: remoteproc@fb204000 { |
| compatible = "qcom,pronto-v2-pil", "qcom,pronto"; |
| reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; |
| reg-names = "ccu", "dxe", "pmu"; |
| |
| memory-region = <&wcnss_region>; |
| |
| interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, |
| <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
| <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
| <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; |
| |
| qcom,smem-states = <&wcnss_smp2p_out 0>; |
| qcom,smem-state-names = "stop"; |
| |
| status = "disabled"; |
| |
| iris { |
| compatible = "qcom,wcn3680"; |
| |
| clocks = <&rpmcc RPM_SMD_CXO_A2>; |
| clock-names = "xo"; |
| }; |
| |
| smd-edge { |
| interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; |
| |
| mboxes = <&apcs 17>; |
| qcom,smd-edge = <6>; |
| |
| wcnss { |
| compatible = "qcom,wcnss"; |
| qcom,smd-channels = "WCNSS_CTRL"; |
| status = "disabled"; |
| |
| qcom,mmio = <&pronto>; |
| |
| bluetooth { |
| compatible = "qcom,wcnss-bt"; |
| }; |
| |
| wifi { |
| compatible = "qcom,wcnss-wlan"; |
| |
| interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "tx", "rx"; |
| |
| qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; |
| qcom,smem-state-names = "tx-enable", |
| "tx-rings-empty"; |
| }; |
| }; |
| }; |
| }; |
| |
| sram@fc190000 { |
| compatible = "qcom,msm8974-rpm-stats"; |
| reg = <0xfc190000 0x10000>; |
| }; |
| |
| etf@fc307000 { |
| compatible = "arm,coresight-tmc", "arm,primecell"; |
| reg = <0xfc307000 0x1000>; |
| |
| clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "atclk"; |
| |
| out-ports { |
| port { |
| etf_out: endpoint { |
| remote-endpoint = <&replicator_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| port { |
| etf_in: endpoint { |
| remote-endpoint = <&merger_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| tpiu@fc318000 { |
| compatible = "arm,coresight-tpiu", "arm,primecell"; |
| reg = <0xfc318000 0x1000>; |
| |
| clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "atclk"; |
| |
| in-ports { |
| port { |
| tpiu_in: endpoint { |
| remote-endpoint = <&replicator_out1>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@fc31a000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0xfc31a000 0x1000>; |
| |
| clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "atclk"; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| /* |
| * Not described input ports: |
| * 0 - not-connected |
| * 1 - connected trought funnel to Multimedia CPU |
| * 2 - connected to Wireless CPU |
| * 3 - not-connected |
| * 4 - not-connected |
| * 6 - not-connected |
| * 7 - connected to STM |
| */ |
| port@5 { |
| reg = <5>; |
| funnel1_in5: endpoint { |
| remote-endpoint = <&kpss_out>; |
| }; |
| }; |
| }; |
| |
| out-ports { |
| port { |
| funnel1_out: endpoint { |
| remote-endpoint = <&merger_in1>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@fc31b000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0xfc31b000 0x1000>; |
| |
| clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "atclk"; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| /* |
| * Not described input ports: |
| * 0 - connected trought funnel to Audio, Modem and |
| * Resource and Power Manager CPU's |
| * 2...7 - not-connected |
| */ |
| port@1 { |
| reg = <1>; |
| merger_in1: endpoint { |
| remote-endpoint = <&funnel1_out>; |
| }; |
| }; |
| }; |
| |
| out-ports { |
| port { |
| merger_out: endpoint { |
| remote-endpoint = <&etf_in>; |
| }; |
| }; |
| }; |
| }; |
| |
| replicator@fc31c000 { |
| compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; |
| reg = <0xfc31c000 0x1000>; |
| |
| clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "atclk"; |
| |
| out-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| replicator_out0: endpoint { |
| remote-endpoint = <&etr_in>; |
| }; |
| }; |
| port@1 { |
| reg = <1>; |
| replicator_out1: endpoint { |
| remote-endpoint = <&tpiu_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| port { |
| replicator_in: endpoint { |
| remote-endpoint = <&etf_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| etr@fc322000 { |
| compatible = "arm,coresight-tmc", "arm,primecell"; |
| reg = <0xfc322000 0x1000>; |
| |
| clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "atclk"; |
| |
| in-ports { |
| port { |
| etr_in: endpoint { |
| remote-endpoint = <&replicator_out0>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@fc33c000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0xfc33c000 0x1000>; |
| |
| clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "atclk"; |
| |
| cpu = <&CPU0>; |
| |
| out-ports { |
| port { |
| etm0_out: endpoint { |
| remote-endpoint = <&kpss_in0>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@fc33d000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0xfc33d000 0x1000>; |
| |
| clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "atclk"; |
| |
| cpu = <&CPU1>; |
| |
| out-ports { |
| port { |
| etm1_out: endpoint { |
| remote-endpoint = <&kpss_in1>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@fc33e000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0xfc33e000 0x1000>; |
| |
| clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "atclk"; |
| |
| cpu = <&CPU2>; |
| |
| out-ports { |
| port { |
| etm2_out: endpoint { |
| remote-endpoint = <&kpss_in2>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@fc33f000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0xfc33f000 0x1000>; |
| |
| clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "atclk"; |
| |
| cpu = <&CPU3>; |
| |
| out-ports { |
| port { |
| etm3_out: endpoint { |
| remote-endpoint = <&kpss_in3>; |
| }; |
| }; |
| }; |
| }; |
| |
| /* KPSS funnel, only 4 inputs are used */ |
| funnel@fc345000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0xfc345000 0x1000>; |
| |
| clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "atclk"; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| kpss_in0: endpoint { |
| remote-endpoint = <&etm0_out>; |
| }; |
| }; |
| port@1 { |
| reg = <1>; |
| kpss_in1: endpoint { |
| remote-endpoint = <&etm1_out>; |
| }; |
| }; |
| port@2 { |
| reg = <2>; |
| kpss_in2: endpoint { |
| remote-endpoint = <&etm2_out>; |
| }; |
| }; |
| port@3 { |
| reg = <3>; |
| kpss_in3: endpoint { |
| remote-endpoint = <&etm3_out>; |
| }; |
| }; |
| }; |
| |
| out-ports { |
| port { |
| kpss_out: endpoint { |
| remote-endpoint = <&funnel1_in5>; |
| }; |
| }; |
| }; |
| }; |
| |
| bimc: interconnect@fc380000 { |
| reg = <0xfc380000 0x6a000>; |
| compatible = "qcom,msm8974-bimc"; |
| #interconnect-cells = <1>; |
| clock-names = "bus", "bus_a"; |
| clocks = <&rpmcc RPM_SMD_BIMC_CLK>, |
| <&rpmcc RPM_SMD_BIMC_A_CLK>; |
| }; |
| |
| gcc: clock-controller@fc400000 { |
| compatible = "qcom,gcc-msm8974"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| reg = <0xfc400000 0x4000>; |
| |
| clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, |
| <&sleep_clk>; |
| clock-names = "xo", |
| "sleep_clk"; |
| }; |
| |
| rpm_msg_ram: sram@fc428000 { |
| compatible = "qcom,rpm-msg-ram"; |
| reg = <0xfc428000 0x4000>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0xfc428000 0x4000>; |
| |
| apss_master_stats: sram@150 { |
| reg = <0x150 0x14>; |
| }; |
| |
| mpss_master_stats: sram@b50 { |
| reg = <0xb50 0x14>; |
| }; |
| |
| lpss_master_stats: sram@1550 { |
| reg = <0x1550 0x14>; |
| }; |
| |
| pronto_master_stats: sram@1f50 { |
| reg = <0x1f50 0x14>; |
| }; |
| }; |
| |
| snoc: interconnect@fc460000 { |
| reg = <0xfc460000 0x4000>; |
| compatible = "qcom,msm8974-snoc"; |
| #interconnect-cells = <1>; |
| clock-names = "bus", "bus_a"; |
| clocks = <&rpmcc RPM_SMD_SNOC_CLK>, |
| <&rpmcc RPM_SMD_SNOC_A_CLK>; |
| }; |
| |
| pnoc: interconnect@fc468000 { |
| reg = <0xfc468000 0x4000>; |
| compatible = "qcom,msm8974-pnoc"; |
| #interconnect-cells = <1>; |
| clock-names = "bus", "bus_a"; |
| clocks = <&rpmcc RPM_SMD_PNOC_CLK>, |
| <&rpmcc RPM_SMD_PNOC_A_CLK>; |
| }; |
| |
| ocmemnoc: interconnect@fc470000 { |
| reg = <0xfc470000 0x4000>; |
| compatible = "qcom,msm8974-ocmemnoc"; |
| #interconnect-cells = <1>; |
| clock-names = "bus", "bus_a"; |
| clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, |
| <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; |
| }; |
| |
| mmssnoc: interconnect@fc478000 { |
| reg = <0xfc478000 0x4000>; |
| compatible = "qcom,msm8974-mmssnoc"; |
| #interconnect-cells = <1>; |
| clock-names = "bus", "bus_a"; |
| clocks = <&mmcc MMSS_S0_AXI_CLK>, |
| <&mmcc MMSS_S0_AXI_CLK>; |
| }; |
| |
| cnoc: interconnect@fc480000 { |
| reg = <0xfc480000 0x4000>; |
| compatible = "qcom,msm8974-cnoc"; |
| #interconnect-cells = <1>; |
| clock-names = "bus", "bus_a"; |
| clocks = <&rpmcc RPM_SMD_CNOC_CLK>, |
| <&rpmcc RPM_SMD_CNOC_A_CLK>; |
| }; |
| |
| tsens: thermal-sensor@fc4a9000 { |
| compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; |
| reg = <0xfc4a9000 0x1000>, /* TM */ |
| <0xfc4a8000 0x1000>; /* SROT */ |
| nvmem-cells = <&tsens_mode>, |
| <&tsens_base1>, <&tsens_base2>, |
| <&tsens_use_backup>, |
| <&tsens_mode_backup>, |
| <&tsens_base1_backup>, <&tsens_base2_backup>, |
| <&tsens_s0_p1>, <&tsens_s0_p2>, |
| <&tsens_s1_p1>, <&tsens_s1_p2>, |
| <&tsens_s2_p1>, <&tsens_s2_p2>, |
| <&tsens_s3_p1>, <&tsens_s3_p2>, |
| <&tsens_s4_p1>, <&tsens_s4_p2>, |
| <&tsens_s5_p1>, <&tsens_s5_p2>, |
| <&tsens_s6_p1>, <&tsens_s6_p2>, |
| <&tsens_s7_p1>, <&tsens_s7_p2>, |
| <&tsens_s8_p1>, <&tsens_s8_p2>, |
| <&tsens_s9_p1>, <&tsens_s9_p2>, |
| <&tsens_s10_p1>, <&tsens_s10_p2>, |
| <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, |
| <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, |
| <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, |
| <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, |
| <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, |
| <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, |
| <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, |
| <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, |
| <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, |
| <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, |
| <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; |
| nvmem-cell-names = "mode", |
| "base1", "base2", |
| "use_backup", |
| "mode_backup", |
| "base1_backup", "base2_backup", |
| "s0_p1", "s0_p2", |
| "s1_p1", "s1_p2", |
| "s2_p1", "s2_p2", |
| "s3_p1", "s3_p2", |
| "s4_p1", "s4_p2", |
| "s5_p1", "s5_p2", |
| "s6_p1", "s6_p2", |
| "s7_p1", "s7_p2", |
| "s8_p1", "s8_p2", |
| "s9_p1", "s9_p2", |
| "s10_p1", "s10_p2", |
| "s0_p1_backup", "s0_p2_backup", |
| "s1_p1_backup", "s1_p2_backup", |
| "s2_p1_backup", "s2_p2_backup", |
| "s3_p1_backup", "s3_p2_backup", |
| "s4_p1_backup", "s4_p2_backup", |
| "s5_p1_backup", "s5_p2_backup", |
| "s6_p1_backup", "s6_p2_backup", |
| "s7_p1_backup", "s7_p2_backup", |
| "s8_p1_backup", "s8_p2_backup", |
| "s9_p1_backup", "s9_p2_backup", |
| "s10_p1_backup", "s10_p2_backup"; |
| #qcom,sensors = <11>; |
| interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "uplow"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| restart@fc4ab000 { |
| compatible = "qcom,pshold"; |
| reg = <0xfc4ab000 0x4>; |
| }; |
| |
| qfprom: efuse@fc4bc000 { |
| compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; |
| reg = <0xfc4bc000 0x2100>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| tsens_base1: base1@d0 { |
| reg = <0xd0 0x1>; |
| bits = <0 8>; |
| }; |
| |
| tsens_s0_p1: s0-p1@d1 { |
| reg = <0xd1 0x1>; |
| bits = <0 6>; |
| }; |
| |
| tsens_s1_p1: s1-p1@d2 { |
| reg = <0xd1 0x2>; |
| bits = <6 6>; |
| }; |
| |
| tsens_s2_p1: s2-p1@d2 { |
| reg = <0xd2 0x2>; |
| bits = <4 6>; |
| }; |
| |
| tsens_s3_p1: s3-p1@d3 { |
| reg = <0xd3 0x1>; |
| bits = <2 6>; |
| }; |
| |
| tsens_s4_p1: s4-p1@d4 { |
| reg = <0xd4 0x1>; |
| bits = <0 6>; |
| }; |
| |
| tsens_s5_p1: s5-p1@d4 { |
| reg = <0xd4 0x2>; |
| bits = <6 6>; |
| }; |
| |
| tsens_s6_p1: s6-p1@d5 { |
| reg = <0xd5 0x2>; |
| bits = <4 6>; |
| }; |
| |
| tsens_s7_p1: s7-p1@d6 { |
| reg = <0xd6 0x1>; |
| bits = <2 6>; |
| }; |
| |
| tsens_s8_p1: s8-p1@d7 { |
| reg = <0xd7 0x1>; |
| bits = <0 6>; |
| }; |
| |
| tsens_mode: mode@d7 { |
| reg = <0xd7 0x1>; |
| bits = <6 2>; |
| }; |
| |
| tsens_s9_p1: s9-p1@d8 { |
| reg = <0xd8 0x1>; |
| bits = <0 6>; |
| }; |
| |
| tsens_s10_p1: s10_p1@d8 { |
| reg = <0xd8 0x2>; |
| bits = <6 6>; |
| }; |
| |
| tsens_base2: base2@d9 { |
| reg = <0xd9 0x2>; |
| bits = <4 8>; |
| }; |
| |
| tsens_s0_p2: s0-p2@da { |
| reg = <0xda 0x2>; |
| bits = <4 6>; |
| }; |
| |
| tsens_s1_p2: s1-p2@db { |
| reg = <0xdb 0x1>; |
| bits = <2 6>; |
| }; |
| |
| tsens_s2_p2: s2-p2@dc { |
| reg = <0xdc 0x1>; |
| bits = <0 6>; |
| }; |
| |
| tsens_s3_p2: s3-p2@dc { |
| reg = <0xdc 0x2>; |
| bits = <6 6>; |
| }; |
| |
| tsens_s4_p2: s4-p2@dd { |
| reg = <0xdd 0x2>; |
| bits = <4 6>; |
| }; |
| |
| tsens_s5_p2: s5-p2@de { |
| reg = <0xde 0x2>; |
| bits = <2 6>; |
| }; |
| |
| tsens_s6_p2: s6-p2@df { |
| reg = <0xdf 0x1>; |
| bits = <0 6>; |
| }; |
| |
| tsens_s7_p2: s7-p2@e0 { |
| reg = <0xe0 0x1>; |
| bits = <0 6>; |
| }; |
| |
| tsens_s8_p2: s8-p2@e0 { |
| reg = <0xe0 0x2>; |
| bits = <6 6>; |
| }; |
| |
| tsens_s9_p2: s9-p2@e1 { |
| reg = <0xe1 0x2>; |
| bits = <4 6>; |
| }; |
| |
| tsens_s10_p2: s10_p2@e2 { |
| reg = <0xe2 0x2>; |
| bits = <2 6>; |
| }; |
| |
| tsens_s5_p2_backup: s5-p2_backup@e3 { |
| reg = <0xe3 0x2>; |
| bits = <0 6>; |
| }; |
| |
| tsens_mode_backup: mode_backup@e3 { |
| reg = <0xe3 0x1>; |
| bits = <6 2>; |
| }; |
| |
| tsens_s6_p2_backup: s6-p2_backup@e4 { |
| reg = <0xe4 0x1>; |
| bits = <0 6>; |
| }; |
| |
| tsens_s7_p2_backup: s7-p2_backup@e4 { |
| reg = <0xe4 0x2>; |
| bits = <6 6>; |
| }; |
| |
| tsens_s8_p2_backup: s8-p2_backup@e5 { |
| reg = <0xe5 0x2>; |
| bits = <4 6>; |
| }; |
| |
| tsens_s9_p2_backup: s9-p2_backup@e6 { |
| reg = <0xe6 0x2>; |
| bits = <2 6>; |
| }; |
| |
| tsens_s10_p2_backup: s10_p2_backup@e7 { |
| reg = <0xe7 0x1>; |
| bits = <0 6>; |
| }; |
| |
| tsens_base1_backup: base1_backup@440 { |
| reg = <0x440 0x1>; |
| bits = <0 8>; |
| }; |
| |
| tsens_s0_p1_backup: s0-p1_backup@441 { |
| reg = <0x441 0x1>; |
| bits = <0 6>; |
| }; |
| |
| tsens_s1_p1_backup: s1-p1_backup@442 { |
| reg = <0x441 0x2>; |
| bits = <6 6>; |
| }; |
| |
| tsens_s2_p1_backup: s2-p1_backup@442 { |
| reg = <0x442 0x2>; |
| bits = <4 6>; |
| }; |
| |
| tsens_s3_p1_backup: s3-p1_backup@443 { |
| reg = <0x443 0x1>; |
| bits = <2 6>; |
| }; |
| |
| tsens_s4_p1_backup: s4-p1_backup@444 { |
| reg = <0x444 0x1>; |
| bits = <0 6>; |
| }; |
| |
| tsens_s5_p1_backup: s5-p1_backup@444 { |
| reg = <0x444 0x2>; |
| bits = <6 6>; |
| }; |
| |
| tsens_s6_p1_backup: s6-p1_backup@445 { |
| reg = <0x445 0x2>; |
| bits = <4 6>; |
| }; |
| |
| tsens_s7_p1_backup: s7-p1_backup@446 { |
| reg = <0x446 0x1>; |
| bits = <2 6>; |
| }; |
| |
| tsens_use_backup: use_backup@447 { |
| reg = <0x447 0x1>; |
| bits = <5 3>; |
| }; |
| |
| tsens_s8_p1_backup: s8-p1_backup@448 { |
| reg = <0x448 0x1>; |
| bits = <0 6>; |
| }; |
| |
| tsens_s9_p1_backup: s9-p1_backup@448 { |
| reg = <0x448 0x2>; |
| bits = <6 6>; |
| }; |
| |
| tsens_s10_p1_backup: s10_p1_backup@449 { |
| reg = <0x449 0x2>; |
| bits = <4 6>; |
| }; |
| |
| tsens_base2_backup: base2_backup@44a { |
| reg = <0x44a 0x2>; |
| bits = <2 8>; |
| }; |
| |
| tsens_s0_p2_backup: s0-p2_backup@44b { |
| reg = <0x44b 0x3>; |
| bits = <2 6>; |
| }; |
| |
| tsens_s1_p2_backup: s1-p2_backup@44c { |
| reg = <0x44c 0x1>; |
| bits = <0 6>; |
| }; |
| |
| tsens_s2_p2_backup: s2-p2_backup@44c { |
| reg = <0x44c 0x2>; |
| bits = <6 6>; |
| }; |
| |
| tsens_s3_p2_backup: s3-p2_backup@44d { |
| reg = <0x44d 0x2>; |
| bits = <4 6>; |
| }; |
| |
| tsens_s4_p2_backup: s4-p2_backup@44e { |
| reg = <0x44e 0x1>; |
| bits = <2 6>; |
| }; |
| }; |
| |
| spmi_bus: spmi@fc4cf000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg-names = "core", "intr", "cnfg"; |
| reg = <0xfc4cf000 0x1000>, |
| <0xfc4cb000 0x1000>, |
| <0xfc4ca000 0x1000>; |
| interrupt-names = "periph_irq"; |
| interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| }; |
| |
| bam_dmux_dma: dma-controller@fc834000 { |
| compatible = "qcom,bam-v1.4.0"; |
| reg = <0xfc834000 0x7000>; |
| interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| #dma-cells = <1>; |
| qcom,ee = <0>; |
| |
| num-channels = <6>; |
| qcom,num-ees = <1>; |
| qcom,powered-remotely; |
| }; |
| |
| remoteproc_mss: remoteproc@fc880000 { |
| compatible = "qcom,msm8974-mss-pil"; |
| reg = <0xfc880000 0x100>, <0xfc820000 0x020>; |
| reg-names = "qdsp6", "rmb"; |
| |
| interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
| <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; |
| |
| clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, |
| <&gcc GCC_MSS_CFG_AHB_CLK>, |
| <&gcc GCC_BOOT_ROM_AHB_CLK>, |
| <&xo_board>; |
| clock-names = "iface", "bus", "mem", "xo"; |
| |
| resets = <&gcc GCC_MSS_RESTART>; |
| reset-names = "mss_restart"; |
| |
| qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>; |
| |
| qcom,smem-states = <&modem_smp2p_out 0>; |
| qcom,smem-state-names = "stop"; |
| |
| status = "disabled"; |
| |
| mba { |
| memory-region = <&mba_region>; |
| }; |
| |
| mpss { |
| memory-region = <&mpss_region>; |
| }; |
| |
| bam_dmux: bam-dmux { |
| compatible = "qcom,bam-dmux"; |
| |
| interrupt-parent = <&modem_smsm>; |
| interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; |
| interrupt-names = "pc", "pc-ack"; |
| |
| qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; |
| qcom,smem-state-names = "pc", "pc-ack"; |
| |
| dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| smd-edge { |
| interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; |
| |
| mboxes = <&apcs 12>; |
| qcom,smd-edge = <0>; |
| |
| label = "modem"; |
| }; |
| }; |
| |
| tcsr_mutex: hwlock@fd484000 { |
| compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon"; |
| reg = <0xfd484000 0x2000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| tcsr: syscon@fd4a0000 { |
| compatible = "qcom,tcsr-msm8974", "syscon"; |
| reg = <0xfd4a0000 0x10000>; |
| }; |
| |
| tlmm: pinctrl@fd510000 { |
| compatible = "qcom,msm8974-pinctrl"; |
| reg = <0xfd510000 0x4000>; |
| gpio-controller; |
| gpio-ranges = <&tlmm 0 0 146>; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| |
| sdc1_off: sdc1-off-state { |
| clk-pins { |
| pins = "sdc1_clk"; |
| bias-disable; |
| drive-strength = <2>; |
| }; |
| |
| cmd-pins { |
| pins = "sdc1_cmd"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| |
| data-pins { |
| pins = "sdc1_data"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| sdc2_off: sdc2-off-state { |
| clk-pins { |
| pins = "sdc2_clk"; |
| bias-disable; |
| drive-strength = <2>; |
| }; |
| |
| cmd-pins { |
| pins = "sdc2_cmd"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| |
| data-pins { |
| pins = "sdc2_data"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| blsp1_uart2_default: blsp1-uart2-default-state { |
| rx-pins { |
| pins = "gpio5"; |
| function = "blsp_uart2"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| tx-pins { |
| pins = "gpio4"; |
| function = "blsp_uart2"; |
| drive-strength = <4>; |
| bias-disable; |
| }; |
| }; |
| |
| blsp2_uart1_default: blsp2-uart1-default-state { |
| tx-rts-pins { |
| pins = "gpio41", "gpio44"; |
| function = "blsp_uart7"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| rx-cts-pins { |
| pins = "gpio42", "gpio43"; |
| function = "blsp_uart7"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| }; |
| |
| blsp2_uart1_sleep: blsp2-uart1-sleep-state { |
| pins = "gpio41", "gpio42", "gpio43", "gpio44"; |
| function = "gpio"; |
| drive-strength = <2>; |
| bias-pull-down; |
| }; |
| |
| blsp2_uart4_default: blsp2-uart4-default-state { |
| tx-rts-pins { |
| pins = "gpio53", "gpio56"; |
| function = "blsp_uart10"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| rx-cts-pins { |
| pins = "gpio54", "gpio55"; |
| function = "blsp_uart10"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| }; |
| |
| blsp1_i2c1_default: blsp1-i2c1-default-state { |
| pins = "gpio2", "gpio3"; |
| function = "blsp_i2c1"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| blsp1_i2c1_sleep: blsp1-i2c1-sleep-state { |
| pins = "gpio2", "gpio3"; |
| function = "blsp_i2c1"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| blsp1_i2c2_default: blsp1-i2c2-default-state { |
| pins = "gpio6", "gpio7"; |
| function = "blsp_i2c2"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { |
| pins = "gpio6", "gpio7"; |
| function = "blsp_i2c2"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| blsp1_i2c3_default: blsp1-i2c3-default-state { |
| pins = "gpio10", "gpio11"; |
| function = "blsp_i2c3"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { |
| pins = "gpio10", "gpio11"; |
| function = "blsp_i2c3"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| /* BLSP1_I2C4 info is missing */ |
| |
| /* BLSP1_I2C5 info is missing */ |
| |
| blsp1_i2c6_default: blsp1-i2c6-default-state { |
| pins = "gpio29", "gpio30"; |
| function = "blsp_i2c6"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { |
| pins = "gpio29", "gpio30"; |
| function = "blsp_i2c6"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ |
| |
| /* BLSP2_I2C1 info is missing */ |
| |
| blsp2_i2c2_default: blsp2-i2c2-default-state { |
| pins = "gpio47", "gpio48"; |
| function = "blsp_i2c8"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { |
| pins = "gpio47", "gpio48"; |
| function = "blsp_i2c8"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| /* BLSP2_I2C3 info is missing */ |
| |
| /* BLSP2_I2C4 info is missing */ |
| |
| blsp2_i2c5_default: blsp2-i2c5-default-state { |
| pins = "gpio83", "gpio84"; |
| function = "blsp_i2c11"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { |
| pins = "gpio83", "gpio84"; |
| function = "blsp_i2c11"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| blsp2_i2c6_default: blsp2-i2c6-default-state { |
| pins = "gpio87", "gpio88"; |
| function = "blsp_i2c12"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { |
| pins = "gpio87", "gpio88"; |
| function = "blsp_i2c12"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| cci_default: cci-default-state { |
| cci_i2c0_default: cci-i2c0-default-pins { |
| pins = "gpio19", "gpio20"; |
| function = "cci_i2c0"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| cci_i2c1_default: cci-i2c1-default-pins { |
| pins = "gpio21", "gpio22"; |
| function = "cci_i2c1"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| cci_sleep: cci-sleep-state { |
| cci_i2c0_sleep: cci-i2c0-sleep-pins { |
| pins = "gpio19", "gpio20"; |
| function = "gpio"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| cci_i2c1_sleep: cci-i2c1-sleep-pins { |
| pins = "gpio21", "gpio22"; |
| function = "gpio"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| spi8_default: spi8_default-state { |
| mosi-pins { |
| pins = "gpio45"; |
| function = "blsp_spi8"; |
| }; |
| miso-pins { |
| pins = "gpio46"; |
| function = "blsp_spi8"; |
| }; |
| cs-pins { |
| pins = "gpio47"; |
| function = "blsp_spi8"; |
| }; |
| clk-pins { |
| pins = "gpio48"; |
| function = "blsp_spi8"; |
| }; |
| }; |
| }; |
| |
| mmcc: clock-controller@fd8c0000 { |
| compatible = "qcom,mmcc-msm8974"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| reg = <0xfd8c0000 0x6000>; |
| clocks = <&xo_board>, |
| <&gcc GCC_MMSS_GPLL0_CLK_SRC>, |
| <&gcc GPLL0_VOTE>, |
| <&gcc GPLL1_VOTE>, |
| <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, |
| <&mdss_dsi0_phy 1>, |
| <&mdss_dsi0_phy 0>, |
| <&mdss_dsi1_phy 1>, |
| <&mdss_dsi1_phy 0>, |
| <0>, |
| <0>, |
| <0>; |
| clock-names = "xo", |
| "mmss_gpll0_vote", |
| "gpll0_vote", |
| "gpll1_vote", |
| "gfx3d_clk_src", |
| "dsi0pll", |
| "dsi0pllbyte", |
| "dsi1pll", |
| "dsi1pllbyte", |
| "hdmipll", |
| "edp_link_clk", |
| "edp_vco_div"; |
| }; |
| |
| mdss: display-subsystem@fd900000 { |
| compatible = "qcom,mdss"; |
| reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; |
| reg-names = "mdss_phys", "vbif_phys"; |
| |
| power-domains = <&mmcc MDSS_GDSC>; |
| |
| clocks = <&mmcc MDSS_AHB_CLK>, |
| <&mmcc MDSS_AXI_CLK>, |
| <&mmcc MDSS_VSYNC_CLK>; |
| clock-names = "iface", "bus", "vsync"; |
| |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| |
| status = "disabled"; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| mdp: display-controller@fd900000 { |
| compatible = "qcom,msm8974-mdp5", "qcom,mdp5"; |
| reg = <0xfd900100 0x22000>; |
| reg-names = "mdp_phys"; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <0>; |
| |
| clocks = <&mmcc MDSS_AHB_CLK>, |
| <&mmcc MDSS_AXI_CLK>, |
| <&mmcc MDSS_MDP_CLK>, |
| <&mmcc MDSS_VSYNC_CLK>; |
| clock-names = "iface", "bus", "core", "vsync"; |
| |
| interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; |
| interconnect-names = "mdp0-mem"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| mdp5_intf1_out: endpoint { |
| remote-endpoint = <&mdss_dsi0_in>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| mdp5_intf2_out: endpoint { |
| remote-endpoint = <&mdss_dsi1_in>; |
| }; |
| }; |
| }; |
| }; |
| |
| mdss_dsi0: dsi@fd922800 { |
| compatible = "qcom,msm8974-dsi-ctrl", |
| "qcom,mdss-dsi-ctrl"; |
| reg = <0xfd922800 0x1f8>; |
| reg-names = "dsi_ctrl"; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <4>; |
| |
| assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; |
| assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; |
| |
| clocks = <&mmcc MDSS_MDP_CLK>, |
| <&mmcc MDSS_AHB_CLK>, |
| <&mmcc MDSS_AXI_CLK>, |
| <&mmcc MDSS_BYTE0_CLK>, |
| <&mmcc MDSS_PCLK0_CLK>, |
| <&mmcc MDSS_ESC0_CLK>, |
| <&mmcc MMSS_MISC_AHB_CLK>; |
| clock-names = "mdp_core", |
| "iface", |
| "bus", |
| "byte", |
| "pixel", |
| "core", |
| "core_mmss"; |
| |
| phys = <&mdss_dsi0_phy>; |
| |
| status = "disabled"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| mdss_dsi0_in: endpoint { |
| remote-endpoint = <&mdp5_intf1_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| mdss_dsi0_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| mdss_dsi0_phy: phy@fd922a00 { |
| compatible = "qcom,dsi-phy-28nm-hpm"; |
| reg = <0xfd922a00 0xd4>, |
| <0xfd922b00 0x280>, |
| <0xfd922d80 0x30>; |
| reg-names = "dsi_pll", |
| "dsi_phy", |
| "dsi_phy_regulator"; |
| |
| #clock-cells = <1>; |
| #phy-cells = <0>; |
| |
| clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; |
| clock-names = "iface", "ref"; |
| |
| status = "disabled"; |
| }; |
| |
| mdss_dsi1: dsi@fd922e00 { |
| compatible = "qcom,msm8974-dsi-ctrl", |
| "qcom,mdss-dsi-ctrl"; |
| reg = <0xfd922e00 0x1f8>; |
| reg-names = "dsi_ctrl"; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <4>; |
| |
| assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; |
| assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; |
| |
| clocks = <&mmcc MDSS_MDP_CLK>, |
| <&mmcc MDSS_AHB_CLK>, |
| <&mmcc MDSS_AXI_CLK>, |
| <&mmcc MDSS_BYTE1_CLK>, |
| <&mmcc MDSS_PCLK1_CLK>, |
| <&mmcc MDSS_ESC1_CLK>, |
| <&mmcc MMSS_MISC_AHB_CLK>; |
| clock-names = "mdp_core", |
| "iface", |
| "bus", |
| "byte", |
| "pixel", |
| "core", |
| "core_mmss"; |
| |
| phys = <&mdss_dsi1_phy>; |
| |
| status = "disabled"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| mdss_dsi1_in: endpoint { |
| remote-endpoint = <&mdp5_intf2_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| mdss_dsi1_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| mdss_dsi1_phy: phy@fd923000 { |
| compatible = "qcom,dsi-phy-28nm-hpm"; |
| reg = <0xfd923000 0xd4>, |
| <0xfd923100 0x280>, |
| <0xfd923380 0x30>; |
| reg-names = "dsi_pll", |
| "dsi_phy", |
| "dsi_phy_regulator"; |
| |
| #clock-cells = <1>; |
| #phy-cells = <0>; |
| |
| clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; |
| clock-names = "iface", "ref"; |
| |
| status = "disabled"; |
| }; |
| }; |
| |
| cci: cci@fda0c000 { |
| compatible = "qcom,msm8974-cci"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xfda0c000 0x1000>; |
| interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&mmcc CAMSS_TOP_AHB_CLK>, |
| <&mmcc CAMSS_CCI_CCI_AHB_CLK>, |
| <&mmcc CAMSS_CCI_CCI_CLK>; |
| clock-names = "camss_top_ahb", |
| "cci_ahb", |
| "cci"; |
| |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&cci_default>; |
| pinctrl-1 = <&cci_sleep>; |
| |
| status = "disabled"; |
| |
| cci_i2c0: i2c-bus@0 { |
| reg = <0>; |
| clock-frequency = <100000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| cci_i2c1: i2c-bus@1 { |
| reg = <1>; |
| clock-frequency = <100000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| gpu: gpu@fdb00000 { |
| compatible = "qcom,adreno-330.1", "qcom,adreno"; |
| reg = <0xfdb00000 0x10000>; |
| reg-names = "kgsl_3d0_reg_memory"; |
| |
| interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "kgsl_3d0_irq"; |
| |
| clocks = <&mmcc OXILI_GFX3D_CLK>, |
| <&mmcc OXILICX_AHB_CLK>, |
| <&mmcc OXILICX_AXI_CLK>; |
| clock-names = "core", "iface", "mem_iface"; |
| |
| sram = <&gmu_sram>; |
| power-domains = <&mmcc OXILICX_GDSC>; |
| operating-points-v2 = <&gpu_opp_table>; |
| |
| interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, |
| <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; |
| interconnect-names = "gfx-mem", "ocmem"; |
| |
| // iommus = <&gpu_iommu 0>; |
| |
| status = "disabled"; |
| |
| gpu_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-320000000 { |
| opp-hz = /bits/ 64 <320000000>; |
| }; |
| |
| opp-200000000 { |
| opp-hz = /bits/ 64 <200000000>; |
| }; |
| |
| opp-27000000 { |
| opp-hz = /bits/ 64 <27000000>; |
| }; |
| }; |
| }; |
| |
| sram@fdd00000 { |
| compatible = "qcom,msm8974-ocmem"; |
| reg = <0xfdd00000 0x2000>, |
| <0xfec00000 0x180000>; |
| reg-names = "ctrl", "mem"; |
| ranges = <0 0xfec00000 0x180000>; |
| clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, |
| <&mmcc OCMEMCX_OCMEMNOC_CLK>; |
| clock-names = "core", "iface"; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| gmu_sram: gmu-sram@0 { |
| reg = <0x0 0x100000>; |
| }; |
| }; |
| |
| remoteproc_adsp: remoteproc@fe200000 { |
| compatible = "qcom,msm8974-adsp-pil"; |
| reg = <0xfe200000 0x100>; |
| |
| interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, |
| <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
| <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
| <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; |
| |
| clocks = <&xo_board>; |
| clock-names = "xo"; |
| |
| memory-region = <&adsp_region>; |
| |
| qcom,smem-states = <&adsp_smp2p_out 0>; |
| qcom,smem-state-names = "stop"; |
| |
| status = "disabled"; |
| |
| smd-edge { |
| interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; |
| |
| mboxes = <&apcs 8>; |
| qcom,smd-edge = <1>; |
| label = "lpass"; |
| }; |
| }; |
| |
| imem: sram@fe805000 { |
| compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; |
| reg = <0xfe805000 0x1000>; |
| |
| reboot-mode { |
| compatible = "syscon-reboot-mode"; |
| offset = <0x65c>; |
| }; |
| }; |
| }; |
| |
| thermal-zones { |
| cpu0-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 5>; |
| |
| trips { |
| cpu_alert0: trip0 { |
| temperature = <75000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| cpu_crit0: trip1 { |
| temperature = <110000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| cpu1-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 6>; |
| |
| trips { |
| cpu_alert1: trip0 { |
| temperature = <75000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| cpu_crit1: trip1 { |
| temperature = <110000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| cpu2-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 7>; |
| |
| trips { |
| cpu_alert2: trip0 { |
| temperature = <75000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| cpu_crit2: trip1 { |
| temperature = <110000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| cpu3-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 8>; |
| |
| trips { |
| cpu_alert3: trip0 { |
| temperature = <75000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| cpu_crit3: trip1 { |
| temperature = <110000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| q6-dsp-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 1>; |
| |
| trips { |
| q6_dsp_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| modemtx-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 2>; |
| |
| trips { |
| modemtx_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| video-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 3>; |
| |
| trips { |
| video_alert0: trip-point0 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| wlan-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 4>; |
| |
| trips { |
| wlan_alert0: trip-point0 { |
| temperature = <105000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| gpu-top-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 9>; |
| |
| trips { |
| gpu1_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| |
| gpu-bottom-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 10>; |
| |
| trips { |
| gpu2_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| clock-frequency = <19200000>; |
| }; |
| }; |
