| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | |
| %YAML 1.2 | |
| --- | |
| $id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml# | |
| $schema: http://devicetree.org/meta-schemas/core.yaml# | |
| title: Axis ARTPEC-8 SoC clock controller | |
| maintainers: | |
| - Jesper Nilsson <jesper.nilsson@axis.com> | |
| description: | | |
| ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit) | |
| units, generating clocks for different domains. Those CMU units are modeled | |
| as separate device tree nodes, and might depend on each other. | |
| The root clock in that root tree is an external clock: OSCCLK (25 MHz). | |
| This external clock must be defined as a fixed-rate clock in dts. | |
| CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and | |
| dividers; all other clocks of function blocks (other CMUs) are usually | |
| derived from CMU_CMU. | |
| Each clock is assigned an identifier and client nodes can use this identifier | |
| to specify the clock which they consume. All clocks available for usage | |
| in clock consumer nodes are defined as preprocessor macros in | |
| 'include/dt-bindings/clock/axis,artpec8-clk.h' header. | |
| properties: | |
| compatible: | |
| enum: | |
| - axis,artpec8-cmu-cmu | |
| - axis,artpec8-cmu-bus | |
| - axis,artpec8-cmu-core | |
| - axis,artpec8-cmu-cpucl | |
| - axis,artpec8-cmu-fsys | |
| - axis,artpec8-cmu-imem | |
| - axis,artpec8-cmu-peri | |
| reg: | |
| maxItems: 1 | |
| clocks: | |
| minItems: 1 | |
| maxItems: 5 | |
| clock-names: | |
| minItems: 1 | |
| maxItems: 5 | |
| "#clock-cells": | |
| const: 1 | |
| required: | |
| - compatible | |
| - reg | |
| - clocks | |
| - clock-names | |
| - "#clock-cells" | |
| allOf: | |
| - if: | |
| properties: | |
| compatible: | |
| const: axis,artpec8-cmu-cmu | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: External reference clock (25 MHz) | |
| clock-names: | |
| items: | |
| - const: fin_pll | |
| - if: | |
| properties: | |
| compatible: | |
| const: axis,artpec8-cmu-bus | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: External reference clock (25 MHz) | |
| - description: CMU_BUS BUS clock (from CMU_CMU) | |
| - description: CMU_BUS DLP clock (from CMU_CMU) | |
| clock-names: | |
| items: | |
| - const: fin_pll | |
| - const: bus | |
| - const: dlp | |
| - if: | |
| properties: | |
| compatible: | |
| const: axis,artpec8-cmu-core | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: External reference clock (25 MHz) | |
| - description: CMU_CORE main clock (from CMU_CMU) | |
| - description: CMU_CORE DLP clock (from CMU_CMU) | |
| clock-names: | |
| items: | |
| - const: fin_pll | |
| - const: main | |
| - const: dlp | |
| - if: | |
| properties: | |
| compatible: | |
| const: axis,artpec8-cmu-cpucl | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: External reference clock (25 MHz) | |
| - description: CMU_CPUCL switch clock (from CMU_CMU) | |
| clock-names: | |
| items: | |
| - const: fin_pll | |
| - const: switch | |
| - if: | |
| properties: | |
| compatible: | |
| const: axis,artpec8-cmu-fsys | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: External reference clock (25 MHz) | |
| - description: CMU_FSYS SCAN0 clock (from CMU_CMU) | |
| - description: CMU_FSYS SCAN1 clock (from CMU_CMU) | |
| - description: CMU_FSYS BUS clock (from CMU_CMU) | |
| - description: CMU_FSYS IP clock (from CMU_CMU) | |
| clock-names: | |
| items: | |
| - const: fin_pll | |
| - const: scan0 | |
| - const: scan1 | |
| - const: bus | |
| - const: ip | |
| - if: | |
| properties: | |
| compatible: | |
| const: axis,artpec8-cmu-imem | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: External reference clock (25 MHz) | |
| - description: CMU_IMEM ACLK clock (from CMU_CMU) | |
| - description: CMU_IMEM JPEG clock (from CMU_CMU) | |
| clock-names: | |
| items: | |
| - const: fin_pll | |
| - const: aclk | |
| - const: jpeg | |
| - if: | |
| properties: | |
| compatible: | |
| const: axis,artpec8-cmu-peri | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: External reference clock (25 MHz) | |
| - description: CMU_PERI IP clock (from CMU_CMU) | |
| - description: CMU_PERI AUDIO clock (from CMU_CMU) | |
| - description: CMU_PERI DISP clock (from CMU_CMU) | |
| clock-names: | |
| items: | |
| - const: fin_pll | |
| - const: ip | |
| - const: audio | |
| - const: disp | |
| additionalProperties: false | |
| examples: | |
| # Clock controller node for CMU_FSYS | |
| - | | |
| #include <dt-bindings/clock/axis,artpec8-clk.h> | |
| cmu_fsys: clock-controller@16c10000 { | |
| compatible = "axis,artpec8-cmu-fsys"; | |
| reg = <0x16c10000 0x4000>; | |
| #clock-cells = <1>; | |
| clocks = <&fin_pll>, | |
| <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>, | |
| <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>, | |
| <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>, | |
| <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>; | |
| clock-names = "fin_pll", "scan0", "scan1", "bus", "ip"; | |
| }; | |
| ... |