Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Andes machine-level software interrupt controller

description:
  In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
  second time with all interrupt sources tied to zero as the software interrupt
  controller (PLIC_SW). PLIC_SW directly connects to the machine-mode
  inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt
  controller is the parent interrupt controller for PLIC_SW. PLIC_SW can
  generate machine-mode inter-processor interrupts through programming its
  registers.

maintainers:
  - Ben Zong-You Xie <ben717@andestech.com>

properties:
  compatible:
    items:
      - enum:
          - andestech,qilai-plicsw
      - const: andestech,plicsw

  reg:
    maxItems: 1

  interrupts-extended:
    minItems: 1
    maxItems: 15872
    description:
      Specifies which harts are connected to the PLIC_SW. Each item must points
      to a riscv,cpu-intc node, which has a riscv cpu node as parent.

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts-extended

examples:
  - |
    interrupt-controller@400000 {
      compatible = "andestech,qilai-plicsw", "andestech,plicsw";
      reg = <0x400000 0x400000>;
      interrupts-extended = <&cpu0intc 3>,
                            <&cpu1intc 3>,
                            <&cpu2intc 3>,
                            <&cpu3intc 3>;
    };