| /* SPDX-License-Identifier: MIT */ | |
| /* Copyright © 2026 Intel Corporation */ | |
| #ifndef _INTEL_OPROM_REGS_H_ | |
| #define _INTEL_OPROM_REGS_H_ | |
| #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) | |
| #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) | |
| #define PRIMARY_SPI_REGIONID _MMIO(0x102084) | |
| #define SPI_STATIC_REGIONS _MMIO(0x102090) | |
| #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) | |
| #define OROM_OFFSET _MMIO(0x1020c0) | |
| #define OROM_OFFSET_MASK REG_GENMASK(20, 16) | |
| #endif |