| /* |
| * Copyright 2023 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: AMD |
| * |
| */ |
| |
| #ifndef __DC_MPCC_DCN401_H__ |
| #define __DC_MPCC_DCN401_H__ |
| #include "dcn30/dcn30_mpc.h" |
| #include "dcn32/dcn32_mpc.h" |
| |
| #define TO_DCN401_MPC(mpc_base) \ |
| container_of(mpc_base, struct dcn401_mpc, base) |
| |
| #define MPC_REG_VARIABLE_LIST_DCN4_01 \ |
| MPC_REG_VARIABLE_LIST_DCN3_0; \ |
| MPC_REG_VARIABLE_LIST_DCN32; \ |
| uint32_t MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \ |
| uint32_t MPCC_MCM_FIRST_GAMUT_REMAP_MODE[MAX_MPCC]; \ |
| uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \ |
| uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A[MAX_MPCC]; \ |
| uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A[MAX_MPCC]; \ |
| uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A[MAX_MPCC]; \ |
| uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A[MAX_MPCC]; \ |
| uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \ |
| uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \ |
| uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B[MAX_MPCC]; \ |
| uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B[MAX_MPCC]; \ |
| uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B[MAX_MPCC]; \ |
| uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B[MAX_MPCC]; \ |
| uint32_t MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \ |
| uint32_t MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \ |
| uint32_t MPCC_MCM_SECOND_GAMUT_REMAP_MODE[MAX_MPCC]; \ |
| uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \ |
| uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A[MAX_MPCC]; \ |
| uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A[MAX_MPCC]; \ |
| uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A[MAX_MPCC]; \ |
| uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A[MAX_MPCC]; \ |
| uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \ |
| uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \ |
| uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B[MAX_MPCC]; \ |
| uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B[MAX_MPCC]; \ |
| uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B[MAX_MPCC]; \ |
| uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B[MAX_MPCC]; \ |
| uint32_t MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \ |
| uint32_t MPCC_MCM_3DLUT_FAST_LOAD_SELECT[MAX_MPCC]; \ |
| uint32_t MPCC_MCM_3DLUT_FAST_LOAD_STATUS[MAX_MPCC] |
| |
| #define MPC_COMMON_MASK_SH_LIST_DCN4_01(mask_sh) \ |
| MPC_COMMON_MASK_SH_LIST_DCN32(mask_sh), \ |
| SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, mask_sh), \ |
| SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE, mask_sh), \ |
| SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C11_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C12_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C13_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C14_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C21_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C22_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM_FIRST_GAMUT_REMAP_C23_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM_FIRST_GAMUT_REMAP_C24_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM_FIRST_GAMUT_REMAP_C31_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM_FIRST_GAMUT_REMAP_C32_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM_FIRST_GAMUT_REMAP_C33_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM_FIRST_GAMUT_REMAP_C34_A, mask_sh), \ |
| SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, mask_sh), \ |
| SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM_SECOND_GAMUT_REMAP_MODE, mask_sh), \ |
| SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM_SECOND_GAMUT_REMAP_C11_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM_SECOND_GAMUT_REMAP_C12_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM_SECOND_GAMUT_REMAP_C13_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM_SECOND_GAMUT_REMAP_C14_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM_SECOND_GAMUT_REMAP_C21_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM_SECOND_GAMUT_REMAP_C22_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM_SECOND_GAMUT_REMAP_C23_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM_SECOND_GAMUT_REMAP_C24_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM_SECOND_GAMUT_REMAP_C31_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM_SECOND_GAMUT_REMAP_C32_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM_SECOND_GAMUT_REMAP_C33_A, mask_sh), \ |
| SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM_SECOND_GAMUT_REMAP_C34_A, mask_sh), \ |
| SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT, MPCC_MCM_3DLUT_FL_SEL, mask_sh), \ |
| SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_DONE, mask_sh), \ |
| SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW, mask_sh), \ |
| SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW, mask_sh) |
| |
| |
| #define MPC_REG_LIST_DCN4_01_RI(inst) \ |
| MPC_REG_LIST_DCN3_2_RI(inst),\ |
| SRII(MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM, inst),\ |
| SRII(MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM, inst),\ |
| SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM, inst),\ |
| SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM, inst),\ |
| SRII(MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM, inst),\ |
| SRII(MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM, inst),\ |
| SRII(MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM, inst),\ |
| SRII(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM, inst),\ |
| SRII(MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B, MPCC_MCM, inst),\ |
| SRII(MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B, MPCC_MCM, inst),\ |
| SRII(MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B, MPCC_MCM, inst),\ |
| SRII(MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B, MPCC_MCM, inst),\ |
| SRII(MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B, MPCC_MCM, inst),\ |
| SRII(MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B, MPCC_MCM, inst),\ |
| SRII(MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM, inst), \ |
| SRII(MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM, inst), \ |
| SRII(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM, inst), \ |
| SRII(MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM, inst), \ |
| SRII(MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM, inst), \ |
| SRII(MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM, inst), \ |
| SRII(MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM, inst), \ |
| SRII(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM, inst), \ |
| SRII(MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B, MPCC_MCM, inst), \ |
| SRII(MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B, MPCC_MCM, inst), \ |
| SRII(MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B, MPCC_MCM, inst), \ |
| SRII(MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B, MPCC_MCM, inst), \ |
| SRII(MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B, MPCC_MCM, inst), \ |
| SRII(MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B, MPCC_MCM, inst), \ |
| SRII(MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM, inst),\ |
| SRII(MPCC_MCM_3DLUT_FAST_LOAD_SELECT, MPCC_MCM, inst) |
| |
| #define MPC_REG_FIELD_LIST_DCN4_01(type)\ |
| MPC_REG_FIELD_LIST_DCN3_0(type);\ |
| MPC_REG_FIELD_LIST_DCN32(type);\ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT;\ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_MODE;\ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT;\ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_C11_A;\ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_C12_A;\ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_C13_A;\ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_C14_A;\ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_C21_A;\ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_C22_A;\ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_C23_A;\ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_C24_A;\ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_C31_A; \ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_C32_A; \ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_C33_A; \ |
| type MPCC_MCM_FIRST_GAMUT_REMAP_C34_A; \ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT;\ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_MODE;\ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT;\ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_C11_A;\ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_C12_A;\ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_C13_A;\ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_C14_A;\ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_C21_A;\ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_C22_A;\ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_C23_A;\ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_C24_A;\ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_C31_A; \ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_C32_A; \ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_C33_A; \ |
| type MPCC_MCM_SECOND_GAMUT_REMAP_C34_A; \ |
| type MPCC_MCM_3DLUT_FL_SEL;\ |
| type MPCC_MCM_3DLUT_FL_DONE;\ |
| type MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW;\ |
| type MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW |
| |
| struct dcn401_mpc_shift { |
| MPC_REG_FIELD_LIST_DCN4_01(uint8_t); |
| }; |
| |
| struct dcn401_mpc_mask { |
| MPC_REG_FIELD_LIST_DCN4_01(uint32_t); |
| }; |
| |
| struct dcn401_mpc_registers { |
| MPC_REG_VARIABLE_LIST_DCN4_01; |
| }; |
| |
| struct dcn401_mpc { |
| struct mpc base; |
| |
| int mpcc_in_use_mask; |
| int num_mpcc; |
| const struct dcn401_mpc_registers *mpc_regs; |
| const struct dcn401_mpc_shift *mpc_shift; |
| const struct dcn401_mpc_mask *mpc_mask; |
| int num_rmu; |
| }; |
| void dcn401_mpc_construct(struct dcn401_mpc *mpc401, |
| struct dc_context *ctx, |
| const struct dcn401_mpc_registers *mpc_regs, |
| const struct dcn401_mpc_shift *mpc_shift, |
| const struct dcn401_mpc_mask *mpc_mask, |
| int num_mpcc, |
| int num_rmu); |
| |
| void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id); |
| void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, |
| bool lut_bank_a, int mpcc_id); |
| |
| void mpc401_program_lut_mode( |
| struct mpc *mpc, |
| const enum MCM_LUT_ID id, |
| const enum MCM_LUT_XABLE xable, |
| bool lut_bank_a, |
| int mpcc_id); |
| |
| void mpc401_program_lut_read_write_control( |
| struct mpc *mpc, |
| const enum MCM_LUT_ID id, |
| bool lut_bank_a, |
| int mpcc_id); |
| |
| void mpc401_program_3dlut_size( |
| struct mpc *mpc, |
| bool is_17x17x17, |
| int mpcc_id); |
| |
| void mpc401_set_gamut_remap( |
| struct mpc *mpc, |
| int mpcc_id, |
| const struct mpc_grph_gamut_adjustment *adjust); |
| |
| void mpc401_get_gamut_remap( |
| struct mpc *mpc, |
| int mpcc_id, |
| struct mpc_grph_gamut_adjustment *adjust); |
| |
| #endif |
