| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
| /* |
| * Device Tree binding constants for AST2700 clock controller. |
| * |
| * Copyright (c) 2024 Aspeed Technology Inc. |
| */ |
| |
| #ifndef __DT_BINDINGS_CLOCK_AST2700_H |
| #define __DT_BINDINGS_CLOCK_AST2700_H |
| |
| /* SOC0 clk */ |
| #define SCU0_CLKIN 0 |
| #define SCU0_CLK_24M 1 |
| #define SCU0_CLK_192M 2 |
| #define SCU0_CLK_UART 3 |
| #define SCU0_CLK_UART_DIV13 3 |
| #define SCU0_CLK_PSP 4 |
| #define SCU0_CLK_HPLL 5 |
| #define SCU0_CLK_HPLL_DIV2 6 |
| #define SCU0_CLK_HPLL_DIV4 7 |
| #define SCU0_CLK_HPLL_DIV_AHB 8 |
| #define SCU0_CLK_DPLL 9 |
| #define SCU0_CLK_MPLL 10 |
| #define SCU0_CLK_MPLL_DIV2 11 |
| #define SCU0_CLK_MPLL_DIV4 12 |
| #define SCU0_CLK_MPLL_DIV8 13 |
| #define SCU0_CLK_MPLL_DIV_AHB 14 |
| #define SCU0_CLK_D0 15 |
| #define SCU0_CLK_D1 16 |
| #define SCU0_CLK_CRT0 17 |
| #define SCU0_CLK_CRT1 18 |
| #define SCU0_CLK_MPHY 19 |
| #define SCU0_CLK_AXI0 20 |
| #define SCU0_CLK_AXI1 21 |
| #define SCU0_CLK_AHB 22 |
| #define SCU0_CLK_APB 23 |
| #define SCU0_CLK_UART4 24 |
| #define SCU0_CLK_EMMCMUX 25 |
| #define SCU0_CLK_EMMC 26 |
| #define SCU0_CLK_U2PHY_CLK12M 27 |
| #define SCU0_CLK_U2PHY_REFCLK 28 |
| |
| /* SOC0 clk-gate */ |
| #define SCU0_CLK_GATE_MCLK 29 |
| #define SCU0_CLK_GATE_ECLK 30 |
| #define SCU0_CLK_GATE_2DCLK 31 |
| #define SCU0_CLK_GATE_VCLK 32 |
| #define SCU0_CLK_GATE_BCLK 33 |
| #define SCU0_CLK_GATE_VGA0CLK 34 |
| #define SCU0_CLK_GATE_REFCLK 35 |
| #define SCU0_CLK_GATE_PORTBUSB2CLK 36 |
| #define SCU0_CLK_GATE_UHCICLK 37 |
| #define SCU0_CLK_GATE_VGA1CLK 38 |
| #define SCU0_CLK_GATE_DDRPHYCLK 39 |
| #define SCU0_CLK_GATE_E2M0CLK 40 |
| #define SCU0_CLK_GATE_HACCLK 41 |
| #define SCU0_CLK_GATE_PORTAUSB2CLK 42 |
| #define SCU0_CLK_GATE_UART4CLK 43 |
| #define SCU0_CLK_GATE_SLICLK 44 |
| #define SCU0_CLK_GATE_DACCLK 45 |
| #define SCU0_CLK_GATE_DP 46 |
| #define SCU0_CLK_GATE_E2M1CLK 47 |
| #define SCU0_CLK_GATE_CRT0CLK 48 |
| #define SCU0_CLK_GATE_CRT1CLK 49 |
| #define SCU0_CLK_GATE_ECDSACLK 50 |
| #define SCU0_CLK_GATE_RSACLK 51 |
| #define SCU0_CLK_GATE_RVAS0CLK 52 |
| #define SCU0_CLK_GATE_UFSCLK 53 |
| #define SCU0_CLK_GATE_EMMCCLK 54 |
| #define SCU0_CLK_GATE_RVAS1CLK 55 |
| |
| /* SOC1 clk */ |
| #define SCU1_CLKIN 0 |
| #define SCU1_CLK_HPLL 1 |
| #define SCU1_CLK_APLL 2 |
| #define SCU1_CLK_APLL_DIV2 3 |
| #define SCU1_CLK_APLL_DIV4 4 |
| #define SCU1_CLK_DPLL 5 |
| #define SCU1_CLK_UXCLK 6 |
| #define SCU1_CLK_HUXCLK 7 |
| #define SCU1_CLK_UARTX 8 |
| #define SCU1_CLK_HUARTX 9 |
| #define SCU1_CLK_AHB 10 |
| #define SCU1_CLK_APB 11 |
| #define SCU1_CLK_UART0 12 |
| #define SCU1_CLK_UART1 13 |
| #define SCU1_CLK_UART2 14 |
| #define SCU1_CLK_UART3 15 |
| #define SCU1_CLK_UART5 16 |
| #define SCU1_CLK_UART6 17 |
| #define SCU1_CLK_UART7 18 |
| #define SCU1_CLK_UART8 19 |
| #define SCU1_CLK_UART9 20 |
| #define SCU1_CLK_UART10 21 |
| #define SCU1_CLK_UART11 22 |
| #define SCU1_CLK_UART12 23 |
| #define SCU1_CLK_UART13 24 |
| #define SCU1_CLK_UART14 25 |
| #define SCU1_CLK_APLL_DIVN 26 |
| #define SCU1_CLK_SDMUX 27 |
| #define SCU1_CLK_SDCLK 28 |
| #define SCU1_CLK_RMII 29 |
| #define SCU1_CLK_RGMII 30 |
| #define SCU1_CLK_MACHCLK 31 |
| #define SCU1_CLK_MAC0RCLK 32 |
| #define SCU1_CLK_MAC1RCLK 33 |
| #define SCU1_CLK_CAN 34 |
| |
| /* SOC1 clk gate */ |
| #define SCU1_CLK_GATE_LCLK0 35 |
| #define SCU1_CLK_GATE_LCLK1 36 |
| #define SCU1_CLK_GATE_ESPI0CLK 37 |
| #define SCU1_CLK_GATE_ESPI1CLK 38 |
| #define SCU1_CLK_GATE_SDCLK 39 |
| #define SCU1_CLK_GATE_IPEREFCLK 40 |
| #define SCU1_CLK_GATE_REFCLK 41 |
| #define SCU1_CLK_GATE_LPCHCLK 42 |
| #define SCU1_CLK_GATE_MAC0CLK 43 |
| #define SCU1_CLK_GATE_MAC1CLK 44 |
| #define SCU1_CLK_GATE_MAC2CLK 45 |
| #define SCU1_CLK_GATE_UART0CLK 46 |
| #define SCU1_CLK_GATE_UART1CLK 47 |
| #define SCU1_CLK_GATE_UART2CLK 48 |
| #define SCU1_CLK_GATE_UART3CLK 49 |
| #define SCU1_CLK_GATE_I2CCLK 50 |
| #define SCU1_CLK_GATE_I3C0CLK 51 |
| #define SCU1_CLK_GATE_I3C1CLK 52 |
| #define SCU1_CLK_GATE_I3C2CLK 53 |
| #define SCU1_CLK_GATE_I3C3CLK 54 |
| #define SCU1_CLK_GATE_I3C4CLK 55 |
| #define SCU1_CLK_GATE_I3C5CLK 56 |
| #define SCU1_CLK_GATE_I3C6CLK 57 |
| #define SCU1_CLK_GATE_I3C7CLK 58 |
| #define SCU1_CLK_GATE_I3C8CLK 59 |
| #define SCU1_CLK_GATE_I3C9CLK 60 |
| #define SCU1_CLK_GATE_I3C10CLK 61 |
| #define SCU1_CLK_GATE_I3C11CLK 62 |
| #define SCU1_CLK_GATE_I3C12CLK 63 |
| #define SCU1_CLK_GATE_I3C13CLK 64 |
| #define SCU1_CLK_GATE_I3C14CLK 65 |
| #define SCU1_CLK_GATE_I3C15CLK 66 |
| #define SCU1_CLK_GATE_UART5CLK 67 |
| #define SCU1_CLK_GATE_UART6CLK 68 |
| #define SCU1_CLK_GATE_UART7CLK 69 |
| #define SCU1_CLK_GATE_UART8CLK 70 |
| #define SCU1_CLK_GATE_UART9CLK 71 |
| #define SCU1_CLK_GATE_UART10CLK 72 |
| #define SCU1_CLK_GATE_UART11CLK 73 |
| #define SCU1_CLK_GATE_UART12CLK 74 |
| #define SCU1_CLK_GATE_FSICLK 75 |
| #define SCU1_CLK_GATE_LTPIPHYCLK 76 |
| #define SCU1_CLK_GATE_LTPICLK 77 |
| #define SCU1_CLK_GATE_VGALCLK 78 |
| #define SCU1_CLK_GATE_UHCICLK 79 |
| #define SCU1_CLK_GATE_CANCLK 80 |
| #define SCU1_CLK_GATE_PCICLK 81 |
| #define SCU1_CLK_GATE_SLICLK 82 |
| #define SCU1_CLK_GATE_E2MCLK 83 |
| #define SCU1_CLK_GATE_PORTCUSB2CLK 84 |
| #define SCU1_CLK_GATE_PORTDUSB2CLK 85 |
| #define SCU1_CLK_GATE_LTPI1TXCLK 86 |
| |
| #endif |
