| // SPDX-License-Identifier: GPL-2.0-or-later OR MIT |
| /* |
| * NXP S32G2 SoC family |
| * |
| * Copyright (c) 2021 SUSE LLC |
| * Copyright 2017-2021, 2024 NXP |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| compatible = "nxp,s32g2"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| scmi_buf: shm@d0000000 { |
| compatible = "arm,scmi-shmem"; |
| reg = <0x0 0xd0000000 0x0 0x80>; |
| no-map; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| next-level-cache = <&cluster0_l2>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x1>; |
| enable-method = "psci"; |
| next-level-cache = <&cluster0_l2>; |
| }; |
| |
| cpu2: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x100>; |
| enable-method = "psci"; |
| next-level-cache = <&cluster1_l2>; |
| }; |
| |
| cpu3: cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x101>; |
| enable-method = "psci"; |
| next-level-cache = <&cluster1_l2>; |
| }; |
| |
| cluster0_l2: l2-cache0 { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| }; |
| |
| cluster1_l2: l2-cache1 { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| firmware { |
| scmi { |
| compatible = "arm,scmi-smc"; |
| arm,smc-id = <0xc20000fe>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| shmem = <&scmi_buf>; |
| |
| clks: protocol@14 { |
| reg = <0x14>; |
| #clock-cells = <1>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| }; |
| |
| soc@0 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0x80000000>; |
| |
| rtc0: rtc@40060000 { |
| compatible = "nxp,s32g2-rtc"; |
| reg = <0x40060000 0x1000>; |
| interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks 54>, <&clks 55>; |
| clock-names = "ipg", "source0"; |
| }; |
| |
| pinctrl: pinctrl@4009c240 { |
| compatible = "nxp,s32g2-siul2-pinctrl"; |
| /* MSCR0-MSCR101 registers on siul2_0 */ |
| reg = <0x4009c240 0x198>, |
| /* MSCR112-MSCR122 registers on siul2_1 */ |
| <0x44010400 0x2c>, |
| /* MSCR144-MSCR190 registers on siul2_1 */ |
| <0x44010480 0xbc>, |
| /* IMCR0-IMCR83 registers on siul2_0 */ |
| <0x4009ca40 0x150>, |
| /* IMCR119-IMCR397 registers on siul2_1 */ |
| <0x44010c1c 0x45c>, |
| /* IMCR430-IMCR495 registers on siul2_1 */ |
| <0x440110f8 0x108>; |
| |
| jtag_pins: jtag-pins { |
| jtag-grp0 { |
| pinmux = <0x0>; |
| input-enable; |
| bias-pull-up; |
| slew-rate = <166>; |
| }; |
| |
| jtag-grp1 { |
| pinmux = <0x11>; |
| slew-rate = <166>; |
| }; |
| |
| jtag-grp2 { |
| pinmux = <0x40>; |
| input-enable; |
| bias-pull-down; |
| slew-rate = <166>; |
| }; |
| |
| jtag-grp3 { |
| pinmux = <0x23c0>, |
| <0x23d0>, |
| <0x2320>; |
| }; |
| |
| jtag-grp4 { |
| pinmux = <0x51>; |
| input-enable; |
| bias-pull-up; |
| slew-rate = <166>; |
| }; |
| }; |
| |
| pinctrl_usdhc0: usdhc0grp-pins { |
| usdhc0-grp0 { |
| pinmux = <0x2e1>, |
| <0x381>; |
| output-enable; |
| bias-pull-down; |
| slew-rate = <150>; |
| }; |
| |
| usdhc0-grp1 { |
| pinmux = <0x2f1>, |
| <0x301>, |
| <0x311>, |
| <0x321>, |
| <0x331>, |
| <0x341>, |
| <0x351>, |
| <0x361>, |
| <0x371>; |
| output-enable; |
| input-enable; |
| bias-pull-up; |
| slew-rate = <150>; |
| }; |
| |
| usdhc0-grp2 { |
| pinmux = <0x391>; |
| output-enable; |
| slew-rate = <150>; |
| }; |
| |
| usdhc0-grp3 { |
| pinmux = <0x3a0>; |
| input-enable; |
| slew-rate = <150>; |
| }; |
| |
| usdhc0-grp4 { |
| pinmux = <0x2032>, |
| <0x2042>, |
| <0x2052>, |
| <0x2062>, |
| <0x2072>, |
| <0x2082>, |
| <0x2092>, |
| <0x20a2>, |
| <0x20b2>, |
| <0x20c2>; |
| }; |
| }; |
| |
| pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { |
| usdhc0-100mhz-grp0 { |
| pinmux = <0x2e1>, |
| <0x381>; |
| output-enable; |
| bias-pull-down; |
| slew-rate = <150>; |
| }; |
| |
| usdhc0-100mhz-grp1 { |
| pinmux = <0x2f1>, |
| <0x301>, |
| <0x311>, |
| <0x321>, |
| <0x331>, |
| <0x341>, |
| <0x351>, |
| <0x361>, |
| <0x371>; |
| output-enable; |
| input-enable; |
| bias-pull-up; |
| slew-rate = <150>; |
| }; |
| |
| usdhc0-100mhz-grp2 { |
| pinmux = <0x391>; |
| output-enable; |
| slew-rate = <150>; |
| }; |
| |
| usdhc0-100mhz-grp3 { |
| pinmux = <0x3a0>; |
| input-enable; |
| slew-rate = <150>; |
| }; |
| |
| usdhc0-100mhz-grp4 { |
| pinmux = <0x2032>, |
| <0x2042>, |
| <0x2052>, |
| <0x2062>, |
| <0x2072>, |
| <0x2082>, |
| <0x2092>, |
| <0x20a2>, |
| <0x20b2>, |
| <0x20c2>; |
| }; |
| }; |
| |
| pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { |
| usdhc0-200mhz-grp0 { |
| pinmux = <0x2e1>, |
| <0x381>; |
| output-enable; |
| bias-pull-down; |
| slew-rate = <208>; |
| }; |
| |
| usdhc0-200mhz-grp1 { |
| pinmux = <0x2f1>, |
| <0x301>, |
| <0x311>, |
| <0x321>, |
| <0x331>, |
| <0x341>, |
| <0x351>, |
| <0x361>, |
| <0x371>; |
| output-enable; |
| input-enable; |
| bias-pull-up; |
| slew-rate = <208>; |
| }; |
| |
| usdhc0-200mhz-grp2 { |
| pinmux = <0x391>; |
| output-enable; |
| slew-rate = <208>; |
| }; |
| |
| usdhc0-200mhz-grp3 { |
| pinmux = <0x3a0>; |
| input-enable; |
| slew-rate = <208>; |
| }; |
| |
| usdhc0-200mhz-grp4 { |
| pinmux = <0x2032>, |
| <0x2042>, |
| <0x2052>, |
| <0x2062>, |
| <0x2072>, |
| <0x2082>, |
| <0x2092>, |
| <0x20a2>, |
| <0x20b2>, |
| <0x20c2>; |
| }; |
| }; |
| }; |
| |
| edma0: dma-controller@40144000 { |
| compatible = "nxp,s32g2-edma"; |
| reg = <0x40144000 0x24000>, |
| <0x4012c000 0x3000>, |
| <0x40130000 0x3000>; |
| #dma-cells = <2>; |
| dma-channels = <32>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx-0-15", |
| "tx-16-31", |
| "err"; |
| clocks = <&clks 63>, <&clks 64>; |
| clock-names = "dmamux0", "dmamux1"; |
| }; |
| |
| can0: can@401b4000 { |
| compatible = "nxp,s32g2-flexcan"; |
| reg = <0x401b4000 0xa000>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "mb-0", "state", "berr", "mb-1"; |
| clocks = <&clks 9>, <&clks 11>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| can1: can@401be000 { |
| compatible = "nxp,s32g2-flexcan"; |
| reg = <0x401be000 0xa000>; |
| interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "mb-0", "state", "berr", "mb-1"; |
| clocks = <&clks 9>, <&clks 11>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| uart0: serial@401c8000 { |
| compatible = "nxp,s32g2-linflexuart", |
| "fsl,s32v234-linflexuart"; |
| reg = <0x401c8000 0x3000>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@401cc000 { |
| compatible = "nxp,s32g2-linflexuart", |
| "fsl,s32v234-linflexuart"; |
| reg = <0x401cc000 0x3000>; |
| interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| |
| usbmisc: usbmisc@44064200 { |
| #index-cells = <1>; |
| compatible = "nxp,s32g2-usbmisc"; |
| reg = <0x44064200 0x200>; |
| }; |
| |
| usbotg: usb@44064000 { |
| compatible = "nxp,s32g2-usb"; |
| reg = <0x44064000 0x200>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, /* OTG Core */ |
| <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; /* OTG Wakeup */ |
| clocks = <&clks 94>, <&clks 95>; |
| fsl,usbmisc = <&usbmisc 0>; |
| ahb-burst-config = <0x3>; |
| tx-burst-size-dword = <0x10>; |
| rx-burst-size-dword = <0x10>; |
| phy_type = "ulpi"; |
| dr_mode = "host"; |
| maximum-speed = "high-speed"; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@401d4000 { |
| compatible = "nxp,s32g2-dspi"; |
| reg = <0x401d4000 0x1000>; |
| interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks 26>; |
| clock-names = "dspi"; |
| spi-num-chipselects = <8>; |
| bus-num = <0>; |
| dmas = <&edma0 0 7>, <&edma0 0 8>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@401d8000 { |
| compatible = "nxp,s32g2-dspi"; |
| reg = <0x401d8000 0x1000>; |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks 26>; |
| clock-names = "dspi"; |
| spi-num-chipselects = <5>; |
| bus-num = <1>; |
| dmas = <&edma0 0 10>, <&edma0 0 11>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@401dc000 { |
| compatible = "nxp,s32g2-dspi"; |
| reg = <0x401dc000 0x1000>; |
| interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks 26>; |
| clock-names = "dspi"; |
| spi-num-chipselects = <5>; |
| bus-num = <2>; |
| dmas = <&edma0 0 13>, <&edma0 0 14>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@401e4000 { |
| compatible = "nxp,s32g2-i2c"; |
| reg = <0x401e4000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks 40>; |
| clock-names = "ipg"; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@401e8000 { |
| compatible = "nxp,s32g2-i2c"; |
| reg = <0x401e8000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks 40>; |
| clock-names = "ipg"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@401ec000 { |
| compatible = "nxp,s32g2-i2c"; |
| reg = <0x401ec000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks 40>; |
| clock-names = "ipg"; |
| status = "disabled"; |
| }; |
| |
| edma1: dma-controller@40244000 { |
| compatible = "nxp,s32g2-edma"; |
| reg = <0x40244000 0x24000>, |
| <0x4022c000 0x3000>, |
| <0x40230000 0x3000>; |
| #dma-cells = <2>; |
| dma-channels = <32>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx-0-15", |
| "tx-16-31", |
| "err"; |
| clocks = <&clks 63>, <&clks 64>; |
| clock-names = "dmamux0", "dmamux1"; |
| }; |
| |
| can2: can@402a8000 { |
| compatible = "nxp,s32g2-flexcan"; |
| reg = <0x402a8000 0xa000>; |
| interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "mb-0", "state", "berr", "mb-1"; |
| clocks = <&clks 9>, <&clks 11>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| can3: can@402b2000 { |
| compatible = "nxp,s32g2-flexcan"; |
| reg = <0x402b2000 0xa000>; |
| interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "mb-0", "state", "berr", "mb-1"; |
| clocks = <&clks 9>, <&clks 11>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@402bc000 { |
| compatible = "nxp,s32g2-linflexuart", |
| "fsl,s32v234-linflexuart"; |
| reg = <0x402bc000 0x3000>; |
| interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@402c8000 { |
| compatible = "nxp,s32g2-dspi"; |
| reg = <0x402c8000 0x1000>; |
| interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks 26>; |
| clock-names = "dspi"; |
| spi-num-chipselects = <5>; |
| bus-num = <3>; |
| dmas = <&edma0 1 7>, <&edma0 1 8>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| spi4: spi@402cc000 { |
| compatible = "nxp,s32g2-dspi"; |
| reg = <0x402cc000 0x1000>; |
| interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks 26>; |
| clock-names = "dspi"; |
| spi-num-chipselects = <5>; |
| bus-num = <4>; |
| dmas = <&edma0 1 10>, <&edma0 1 11>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| spi5: spi@402d0000 { |
| compatible = "nxp,s32g2-dspi"; |
| reg = <0x402d0000 0x1000>; |
| interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks 26>; |
| clock-names = "dspi"; |
| spi-num-chipselects = <5>; |
| bus-num = <5>; |
| dmas = <&edma0 1 13>, <&edma0 1 14>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@402d8000 { |
| compatible = "nxp,s32g2-i2c"; |
| reg = <0x402d8000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks 40>; |
| clock-names = "ipg"; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@402dc000 { |
| compatible = "nxp,s32g2-i2c"; |
| reg = <0x402dc000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks 40>; |
| clock-names = "ipg"; |
| status = "disabled"; |
| }; |
| |
| usdhc0: mmc@402f0000 { |
| compatible = "nxp,s32g2-usdhc"; |
| reg = <0x402f0000 0x1000>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks 32>, <&clks 31>, <&clks 33>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <8>; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@50800000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x50800000 0x10000>, |
| <0x50880000 0x80000>, |
| <0x50400000 0x2000>, |
| <0x50410000 0x2000>, |
| <0x50420000 0x2000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| }; |
| }; |
| }; |
