arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts

// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
/*
 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
 */

/dts-v1/;
#include "imx6ul.dtsi"
#include "imx6ul-tx6ul.dtsi"

/ {
	model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard";
	compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";

	aliases {
		lcdif-24bit-pins-a = &pinctrl_disp0_3;
		mmc0 = &usdhc1;
		/delete-property/ mmc1;
		serial2 = &uart3;
		serial4 = &uart5;
	};
	/delete-node/ sound;
};

&can1 {
	xceiver-supply = <&reg_3v3>;
};

&can2 {
	xceiver-supply = <&reg_3v3>;
};

&ds1339 {
	status = "disabled";
};

&fec1 {
	pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>;
	/delete-node/ mdio;
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>;
	phy-mode = "rmii";
	phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
	phy-supply = <&reg_3v3_etn>;
	phy-handle = <&etnphy1>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		etnphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_etnphy0_int>;
			interrupt-parent = <&gpio5>;
			interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
			interrupts-extended = <&gpio5 5 IRQ_TYPE_EDGE_FALLING>;
			status = "okay";
		};

		etnphy1: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <2>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_etnphy1_int>;
			interrupt-parent = <&gpio4>;
			interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
			interrupts-extended = <&gpio4 27 IRQ_TYPE_EDGE_FALLING>;
			status = "okay";
		};
	};
};

&i2c_gpio {
	status = "disabled";
};

&i2c2 {
	/delete-node/ codec@a;
	/delete-node/ touchscreen@48;

	rtc: rtc@6f {
		compatible = "microchip,mcp7940x";
		reg = <0x6f>;
	};
};

&kpp {
	status = "disabled";
};

&lcdif {
	pinctrl-0 = <&pinctrl_disp0_3>;
};

&reg_usbotg_vbus {
	status = "disabled";
};

&usdhc1 {
	pinctrl-0 = <&pinctrl_usdhc1>;
	non-removable;
	/delete-property/ cd-gpios;
	cap-sdio-irq;
};

&uart1 {
	pinctrl-0 = <&pinctrl_uart1>;
	/delete-property/ uart-has-rtscts;
};

&uart2 {
	pinctrl-0 = <&pinctrl_uart2>;
	/delete-property/ uart-has-rtscts;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
};

&uart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart6>;
	status = "okay";
};

&uart7 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart7>;
	status = "okay";
};

&uart8 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart8>;
	status = "disabled"; /* conflicts with LCDIF */
};

&iomuxc {
	hoggrp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x0b0b0 /* WLAN_RESET */
		>;
	};

	pinctrl_disp0_3: disp0-3-grp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x10 /* LSCLK */
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x10 /* OE_ACD */
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x10 /* HSYNC */
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x10 /* VSYNC */
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x10
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x10
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x10
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x10
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x10
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x10
			/* LCD_DATA08..09 not wired */
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x10
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x10
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x10
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x10
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x10
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x10
			/* LCD_DATA16..17 not wired */
			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18	0x10
			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19	0x10
			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20	0x10
			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21	0x10
			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22	0x10
			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23	0x10
		>;
	};

	pinctrl_enet2_mdio: enet2-mdiogrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x0b0b0
			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x0b0b0
			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x0b0b0
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX	0x0b0b0
			MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX	0x0b0b0
		>;
	};

	pinctrl_uart6: uart6grp {
		fsl,pins = <
			MX6UL_PAD_CSI_MCLK__UART6_DCE_TX	0x0b0b0
			MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX	0x0b0b0
		>;
	};

	pinctrl_uart7: uart7grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA16__UART7_DCE_TX	0x0b0b0
			MX6UL_PAD_LCD_DATA17__UART7_DCE_RX	0x0b0b0
		>;
	};

	pinctrl_uart8: uart8grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA20__UART8_DCE_TX	0x0b0b0
			MX6UL_PAD_LCD_DATA21__UART8_DCE_RX	0x0b0b0
		>;
	};
};