Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/amd,versal2-mdb-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller

maintainers:
  - Thippeswamy Havalige <thippeswamy.havalige@amd.com>

allOf:
  - $ref: /schemas/pci/pci-host-bridge.yaml#
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
    const: amd,versal2-mdb-host

  reg:
    items:
      - description: MDB System Level Control and Status Register (SLCR) Base
      - description: configuration region
      - description: data bus interface
      - description: address translation unit register

  reg-names:
    items:
      - const: slcr
      - const: config
      - const: dbi
      - const: atu

  ranges:
    maxItems: 2

  msi-map:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-map-mask:
    items:
      - const: 0
      - const: 0
      - const: 0
      - const: 7

  interrupt-map:
    maxItems: 4

  "#interrupt-cells":
    const: 1

  interrupt-controller:
    description: identifies the node as an interrupt controller
    type: object
    additionalProperties: false
    properties:
      interrupt-controller: true

      "#address-cells":
        const: 0

      "#interrupt-cells":
        const: 1

    required:
      - interrupt-controller
      - "#address-cells"
      - "#interrupt-cells"

required:
  - reg
  - reg-names
  - interrupts
  - interrupt-map
  - interrupt-map-mask
  - msi-map
  - "#interrupt-cells"
  - interrupt-controller

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;
        pcie@ed931000 {
            compatible = "amd,versal2-mdb-host";
            reg = <0x0 0xed931000 0x0 0x2000>,
                  <0x1000 0x100000 0x0 0xff00000>,
                  <0x1000 0x0 0x0 0x1000>,
                  <0x0 0xed860000 0x0 0x2000>;
            reg-names = "slcr", "config", "dbi", "atu";
            ranges = <0x2000000 0x00 0xa0000000 0x00 0xa0000000 0x00 0x10000000>,
                     <0x43000000 0x1100 0x00 0x1100 0x00 0x00 0x1000000>;
            interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-parent = <&gic>;
            interrupt-map-mask = <0 0 0 7>;
            interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
                            <0 0 0 2 &pcie_intc_0 1>,
                            <0 0 0 3 &pcie_intc_0 2>,
                            <0 0 0 4 &pcie_intc_0 3>;
            msi-map = <0x0 &gic_its 0x00 0x10000>;
            #address-cells = <3>;
            #size-cells = <2>;
            #interrupt-cells = <1>;
            device_type = "pci";
            pcie_intc_0: interrupt-controller {
                #address-cells = <0>;
                #interrupt-cells = <1>;
                interrupt-controller;
           };
        };
    };