|  | # SPDX-License-Identifier: GPL-2.0-only | 
|  | config PINCTRL_ASPEED | 
|  | bool | 
|  | depends on (ARCH_ASPEED || COMPILE_TEST) && OF | 
|  | depends on MFD_SYSCON | 
|  | select PINMUX | 
|  | select PINCONF | 
|  | select GENERIC_PINCONF | 
|  | select REGMAP_MMIO | 
|  |  | 
|  | config PINCTRL_ASPEED_G4 | 
|  | bool "Aspeed G4 SoC pin control" | 
|  | depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF | 
|  | select PINCTRL_ASPEED | 
|  | help | 
|  | Say Y here to enable pin controller support for Aspeed's 4th | 
|  | generation SoCs. GPIO is provided by a separate GPIO driver. | 
|  |  | 
|  | config PINCTRL_ASPEED_G5 | 
|  | bool "Aspeed G5 SoC pin control" | 
|  | depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF | 
|  | select PINCTRL_ASPEED | 
|  | help | 
|  | Say Y here to enable pin controller support for Aspeed's 5th | 
|  | generation SoCs. GPIO is provided by a separate GPIO driver. | 
|  |  | 
|  | config PINCTRL_ASPEED_G6 | 
|  | bool "Aspeed G6 SoC pin control" | 
|  | depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF | 
|  | select PINCTRL_ASPEED | 
|  | help | 
|  | Say Y here to enable pin controller support for Aspeed's 6th | 
|  | generation SoCs. GPIO is provided by a separate GPIO driver. |