Documentation/devicetree/bindings/gpio/ti,keystone-dsp-gpio.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/ti,keystone-dsp-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Keystone 2 DSP GPIO controller

maintainers:
  - Grygorii Strashko <grygorii.strashko@ti.com>

description: |
  HOST OS userland running on ARM can send interrupts to DSP cores using
  the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
  This is one of the component used by the IPC mechanism used on Keystone SOCs.

  For example TCI6638K2K SoC has 8 DSP GPIO controllers:
   - 8 for C66x CorePacx CPUs 0-7

  Keystone 2 DSP GPIO controller has specific features:
  - each GPIO can be configured only as output pin;
  - setting GPIO value to 1 causes IRQ generation on target DSP core;
  - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
    pending.

properties:
  compatible:
    const: ti,keystone-dsp-gpio

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2

  gpio,syscon-dev:
    description:
      Phandle and offset of device's specific registers within the syscon state
      control registers
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to syscon
          - description: register offset within state control registers

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'
  - gpio,syscon-dev

additionalProperties: false

examples:
  - |
    gpio@240 {
        compatible = "ti,keystone-dsp-gpio";
        reg = <0x240 0x4>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio,syscon-dev = <&devctrl 0x240>;
    };