| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| # Copyright 2025 Analog Devices Inc. |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/iio/adc/adi,ad7191.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Analog Devices AD7191 ADC |
| |
| maintainers: |
| - Alisa-Dariana Roman <alisa.roman@analog.com> |
| |
| description: | |
| Bindings for the Analog Devices AD7191 ADC device. Datasheet can be |
| found here: |
| https://www.analog.com/media/en/technical-documentation/data-sheets/AD7191.pdf |
| The device's PDOWN pin must be connected to the SPI controller's chip select |
| pin. |
| |
| properties: |
| compatible: |
| enum: |
| - adi,ad7191 |
| |
| reg: |
| maxItems: 1 |
| |
| spi-cpol: true |
| |
| spi-cpha: true |
| |
| clocks: |
| maxItems: 1 |
| description: |
| Must be present when CLKSEL pin is tied HIGH to select external clock |
| source (either a crystal between MCLK1 and MCLK2 pins, or a |
| CMOS-compatible clock driving MCLK2 pin). Must be absent when CLKSEL pin |
| is tied LOW to use the internal 4.92MHz clock. |
| |
| interrupts: |
| maxItems: 1 |
| |
| avdd-supply: |
| description: AVdd voltage supply |
| |
| dvdd-supply: |
| description: DVdd voltage supply |
| |
| vref-supply: |
| description: Vref voltage supply |
| |
| odr-gpios: |
| description: |
| ODR1 and ODR2 pins for output data rate selection. Should be defined if |
| adi,odr-value is absent. |
| minItems: 2 |
| maxItems: 2 |
| |
| adi,odr-value: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Should be present if ODR pins are pin-strapped. Possible values: |
| 120 Hz (ODR1=0, ODR2=0) |
| 60 Hz (ODR1=0, ODR2=1) |
| 50 Hz (ODR1=1, ODR2=0) |
| 10 Hz (ODR1=1, ODR2=1) |
| If defined, odr-gpios must be absent. |
| enum: [120, 60, 50, 10] |
| |
| pga-gpios: |
| description: |
| PGA1 and PGA2 pins for gain selection. Should be defined if adi,pga-value |
| is absent. |
| minItems: 2 |
| maxItems: 2 |
| |
| adi,pga-value: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Should be present if PGA pins are pin-strapped. Possible values: |
| Gain 1 (PGA1=0, PGA2=0) |
| Gain 8 (PGA1=0, PGA2=1) |
| Gain 64 (PGA1=1, PGA2=0) |
| Gain 128 (PGA1=1, PGA2=1) |
| If defined, pga-gpios must be absent. |
| enum: [1, 8, 64, 128] |
| |
| temp-gpios: |
| description: TEMP pin for temperature sensor enable. |
| maxItems: 1 |
| |
| chan-gpios: |
| description: CHAN pin for input channel selection. |
| maxItems: 1 |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| - avdd-supply |
| - dvdd-supply |
| - vref-supply |
| - spi-cpol |
| - spi-cpha |
| - temp-gpios |
| - chan-gpios |
| |
| allOf: |
| - $ref: /schemas/spi/spi-peripheral-props.yaml# |
| - oneOf: |
| - required: |
| - adi,odr-value |
| - required: |
| - odr-gpios |
| - oneOf: |
| - required: |
| - adi,pga-value |
| - required: |
| - pga-gpios |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| spi { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| adc@0 { |
| compatible = "adi,ad7191"; |
| reg = <0>; |
| spi-max-frequency = <1000000>; |
| spi-cpol; |
| spi-cpha; |
| clocks = <&ad7191_mclk>; |
| interrupts = <25 IRQ_TYPE_EDGE_FALLING>; |
| interrupt-parent = <&gpio>; |
| avdd-supply = <&avdd>; |
| dvdd-supply = <&dvdd>; |
| vref-supply = <&vref>; |
| adi,pga-value = <1>; |
| odr-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>, <&gpio 24 GPIO_ACTIVE_HIGH>; |
| temp-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; |
| chan-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; |
| }; |
| }; |