Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/fsl,imx8qxp-isi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX8QXP Image Sensing Interface

maintainers:
  - Frank Li <Frank.Li@nxp.com>

description:
  The Image Sensing Interface (ISI) combines image processing pipelines with
  DMA engines to process and capture frames originating from a variety of
  sources. The inputs to the ISI go through Pixel Link interfaces, and their
  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.

properties:
  compatible:
    enum:
      - fsl,imx8qxp-isi

  reg:
    maxItems: 1

  clocks:
    maxItems: 6

  clock-names:
    items:
      - const: per0
      - const: per1
      - const: per2
      - const: per3
      - const: per4
      - const: per5

  interrupts:
    maxItems: 6

  power-domains:
    maxItems: 6

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    properties:
      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: MIPI CSI-2 RX 0
      port@6:
        $ref: /schemas/graph.yaml#/properties/port
        description: CSI-2 Parallel RX

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts
  - power-domains
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/imx8-clock.h>
    #include <dt-bindings/clock/imx8-lpcg.h>
    #include <dt-bindings/firmware/imx/rsrc.h>

    image-controller@58100000 {
        compatible = "fsl,imx8qxp-isi";
        reg = <0x58100000 0x60000>;
        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
                 <&pdma1_lpcg IMX_LPCG_CLK_0>,
                 <&pdma2_lpcg IMX_LPCG_CLK_0>,
                 <&pdma3_lpcg IMX_LPCG_CLK_0>,
                 <&pdma4_lpcg IMX_LPCG_CLK_0>,
                 <&pdma5_lpcg IMX_LPCG_CLK_0>;
        clock-names = "per0", "per1", "per2", "per3", "per4", "per5";
        power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>,
                        <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>,
                        <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@2 {
                reg = <2>;
                endpoint {
                    remote-endpoint = <&mipi_csi0_out>;
                };
            };
        };
    };
...