| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/spi/st,stm32mp25-ospi.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: STMicroelectronics STM32 Octal Serial Peripheral Interface (OSPI) |
| |
| maintainers: |
| - Patrice Chotard <patrice.chotard@foss.st.com> |
| |
| allOf: |
| - $ref: spi-controller.yaml# |
| |
| properties: |
| compatible: |
| const: st,stm32mp25-ospi |
| |
| reg: |
| maxItems: 1 |
| |
| memory-region: |
| description: |
| Memory region to be used for memory-map read access. |
| In memory-mapped mode, read access are performed from the memory |
| device using the direct mapping. |
| maxItems: 1 |
| |
| clocks: |
| maxItems: 1 |
| |
| interrupts: |
| maxItems: 1 |
| |
| resets: |
| items: |
| - description: phandle to OSPI block reset |
| - description: phandle to delay block reset |
| |
| dmas: |
| maxItems: 2 |
| |
| dma-names: |
| items: |
| - const: tx |
| - const: rx |
| |
| st,syscfg-dlyb: |
| description: configure OCTOSPI delay block. |
| $ref: /schemas/types.yaml#/definitions/phandle-array |
| items: |
| - description: phandle to syscfg |
| - description: register offset within syscfg |
| |
| access-controllers: |
| description: phandle to the rifsc device to check access right |
| and in some cases, an additional phandle to the rcc device for |
| secure clock control. |
| items: |
| - description: phandle to bus controller |
| - description: phandle to clock controller |
| minItems: 1 |
| |
| power-domains: |
| maxItems: 1 |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| - resets |
| - interrupts |
| - st,syscfg-dlyb |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/st,stm32mp25-rcc.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/reset/st,stm32mp25-rcc.h> |
| |
| spi@40430000 { |
| compatible = "st,stm32mp25-ospi"; |
| reg = <0x40430000 0x400>; |
| memory-region = <&mm_ospi1>; |
| interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&hpdma 2 0x62 0x00003121 0x0>, |
| <&hpdma 2 0x42 0x00003112 0x0>; |
| dma-names = "tx", "rx"; |
| clocks = <&scmi_clk CK_SCMI_OSPI1>; |
| resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>; |
| access-controllers = <&rifsc 74>; |
| power-domains = <&CLUSTER_PD>; |
| st,syscfg-dlyb = <&syscfg 0x1000>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| flash@0 { |
| compatible = "jedec,spi-nor"; |
| reg = <0>; |
| spi-rx-bus-width = <4>; |
| spi-max-frequency = <108000000>; |
| }; |
| }; |