| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| * |
| * Copyright (C) 2024 Renesas Electronics Corp. |
| */ |
| #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ |
| #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ |
| |
| #include <dt-bindings/clock/renesas-cpg-mssr.h> |
| |
| /* Core Clock list */ |
| #define R9A09G047_SYS_0_PCLK 0 |
| #define R9A09G047_CA55_0_CORECLK0 1 |
| #define R9A09G047_CA55_0_CORECLK1 2 |
| #define R9A09G047_CA55_0_CORECLK2 3 |
| #define R9A09G047_CA55_0_CORECLK3 4 |
| #define R9A09G047_CA55_0_PERIPHCLK 5 |
| #define R9A09G047_CM33_CLK0 6 |
| #define R9A09G047_CST_0_SWCLKTCK 7 |
| #define R9A09G047_IOTOP_0_SHCLK 8 |
| #define R9A09G047_SPI_CLK_SPI 9 |
| #define R9A09G047_GBETH_0_CLK_PTP_REF_I 10 |
| #define R9A09G047_GBETH_1_CLK_PTP_REF_I 11 |
| #define R9A09G047_USB3_0_REF_ALT_CLK_P 12 |
| #define R9A09G047_USB3_0_CLKCORE 13 |
| #define R9A09G047_USB2_0_CLK_CORE0 14 |
| #define R9A09G047_USB2_0_CLK_CORE1 15 |
| |
| #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ |
