| Device tree configuration for the I2C busses on the AST24XX and AST25XX SoCs. |
| |
| Required Properties: |
| - #address-cells : should be 1 |
| - #size-cells : should be 0 |
| - reg : Address offset and range of bus registers. |
| An additional SRAM buffer address offset and range is |
| optional in case of enabling I2C dedicated SRAM for |
| buffer mode transfer support. |
| - compatible : should be "aspeed,ast2400-i2c-bus" |
| or "aspeed,ast2500-i2c-bus" |
| - clocks : root clock of bus, should reference the APB |
| clock in the second cell |
| - resets : phandle to reset controller with the reset number in |
| the second cell |
| - interrupts : interrupt number |
| |
| Optional Properties: |
| - bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not |
| specified |
| - multi-master : states that there is another master active on this bus. |
| - aspeed,dma-buf-size : size of DMA buffer (from 2 to 4095 in case of AST2500) |
| Only AST2500 supports DMA mode under some limitations: |
| I2C is sharing the DMA H/W with UHCI host controller |
| and MCTP controller. Since those controllers operate |
| with DMA mode only, I2C has to use buffer mode or byte |
| mode instead if one of those controllers is enabled. |
| Also make sure that if SD/eMMC or Port80 snoop uses |
| DMA mode instead of PIO or FIFO respectively, I2C |
| can't use DMA mode. IF both DMA and buffer modes are |
| enabled, DMA mode will be selected. |
| |
| Example: |
| |
| i2c { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x1e78a000 0x1000>; |
| |
| i2c_gr: i2c-global-regs@0 { |
| compatible = "aspeed,ast2500-i2c-gr", "syscon"; |
| reg = <0x0 0x40>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0x40>; |
| |
| i2c_ic: interrupt-controller@0 { |
| #interrupt-cells = <1>; |
| compatible = "aspeed,ast2500-i2c-ic"; |
| reg = <0x0 0x4>; |
| interrupts = <12>; |
| interrupt-controller; |
| }; |
| }; |
| |
| i2c0: i2c-bus@40 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #interrupt-cells = <1>; |
| reg = <0x40 0x40>; |
| compatible = "aspeed,ast2500-i2c-bus"; |
| clocks = <&syscon ASPEED_CLK_APB>; |
| resets = <&syscon ASPEED_RESET_I2C>; |
| bus-frequency = <100000>; |
| interrupts = <0>; |
| interrupt-parent = <&i2c_ic>; |
| }; |
| |
| /* buffer mode transfer enabled */ |
| i2c1: i2c-bus@80 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #interrupt-cells = <1>; |
| reg = <0x80 0x40>, <0x210 0x10>; |
| compatible = "aspeed,ast2500-i2c-bus"; |
| clocks = <&syscon ASPEED_CLK_APB>; |
| resets = <&syscon ASPEED_RESET_I2C>; |
| bus-frequency = <100000>; |
| interrupts = <1>; |
| interrupt-parent = <&i2c_ic>; |
| }; |
| |
| /* DMA mode transfer enabled */ |
| i2c2: i2c-bus@c0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #interrupt-cells = <1>; |
| reg = <0xc0 0x40>; |
| aspeed,dma-buf-size = <4095>; |
| compatible = "aspeed,ast2500-i2c-bus"; |
| clocks = <&syscon ASPEED_CLK_APB>; |
| resets = <&syscon ASPEED_RESET_I2C>; |
| bus-frequency = <100000>; |
| interrupts = <2>; |
| interrupt-parent = <&i2c_ic>; |
| }; |
| }; |
