| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (C) 2018 Xilinx, Inc. |
| */ |
| |
| #ifndef _DT_BINDINGS_ZYNQMP_POWER_H |
| #define _DT_BINDINGS_ZYNQMP_POWER_H |
| |
| #define PD_USB_0 22 |
| #define PD_USB_1 23 |
| #define PD_TTC_0 24 |
| #define PD_TTC_1 25 |
| #define PD_TTC_2 26 |
| #define PD_TTC_3 27 |
| #define PD_SATA 28 |
| #define PD_ETH_0 29 |
| #define PD_ETH_1 30 |
| #define PD_ETH_2 31 |
| #define PD_ETH_3 32 |
| #define PD_UART_0 33 |
| #define PD_UART_1 34 |
| #define PD_SPI_0 35 |
| #define PD_SPI_1 36 |
| #define PD_I2C_0 37 |
| #define PD_I2C_1 38 |
| #define PD_SD_0 39 |
| #define PD_SD_1 40 |
| #define PD_DP 41 |
| #define PD_GDMA 42 |
| #define PD_ADMA 43 |
| #define PD_NAND 44 |
| #define PD_QSPI 45 |
| #define PD_GPIO 46 |
| #define PD_CAN_0 47 |
| #define PD_CAN_1 48 |
| #define PD_GPU 58 |
| #define PD_PCIE 59 |
| |
| #endif |
