| /* SPDX-License-Identifier: GPL-2.0+ |
| * |
| * Copyright (C) 2015 Renesas Electronics Corp. |
| */ |
| |
| #ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ |
| #define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ |
| |
| #include <dt-bindings/clock/renesas-cpg-mssr.h> |
| |
| /* r8a7790 CPG Core Clocks */ |
| #define R8A7790_CLK_Z 0 |
| #define R8A7790_CLK_Z2 1 |
| #define R8A7790_CLK_ZG 2 |
| #define R8A7790_CLK_ZTR 3 |
| #define R8A7790_CLK_ZTRD2 4 |
| #define R8A7790_CLK_ZT 5 |
| #define R8A7790_CLK_ZX 6 |
| #define R8A7790_CLK_ZS 7 |
| #define R8A7790_CLK_HP 8 |
| #define R8A7790_CLK_I 9 |
| #define R8A7790_CLK_B 10 |
| #define R8A7790_CLK_LB 11 |
| #define R8A7790_CLK_P 12 |
| #define R8A7790_CLK_CL 13 |
| #define R8A7790_CLK_M2 14 |
| #define R8A7790_CLK_ADSP 15 |
| #define R8A7790_CLK_IMP 16 |
| #define R8A7790_CLK_ZB3 17 |
| #define R8A7790_CLK_ZB3D2 18 |
| #define R8A7790_CLK_DDR 19 |
| #define R8A7790_CLK_SDH 20 |
| #define R8A7790_CLK_SD0 21 |
| #define R8A7790_CLK_SD1 22 |
| #define R8A7790_CLK_SD2 23 |
| #define R8A7790_CLK_SD3 24 |
| #define R8A7790_CLK_MMC0 25 |
| #define R8A7790_CLK_MMC1 26 |
| #define R8A7790_CLK_MP 27 |
| #define R8A7790_CLK_SSP 28 |
| #define R8A7790_CLK_SSPRS 29 |
| #define R8A7790_CLK_QSPI 30 |
| #define R8A7790_CLK_CP 31 |
| #define R8A7790_CLK_RCAN 32 |
| #define R8A7790_CLK_R 33 |
| #define R8A7790_CLK_OSC 34 |
| |
| #endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */ |
