Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/atmel,at91sam9g45-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Atmel Direct Memory Access Controller (DMA)

maintainers:
  - Ludovic Desroches <ludovic.desroches@microchip.com>

description:
  The Atmel Direct Memory Access Controller (DMAC) transfers data from a source
  peripheral to a destination peripheral over one or more AMBA buses. One channel
  is required for each source/destination pair. In the most basic configuration,
  the DMAC has one master interface and one channel. The master interface reads
  the data from a source and writes it to a destination. Two AMBA transfers are
  required for each DMAC data transfer. This is also known as a dual-access transfer.
  The DMAC is programmed via the APB interface.

properties:
  compatible:
    enum:
      - atmel,at91sam9g45-dma
      - atmel,at91sam9rl-dma

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  "#dma-cells":
    description:
      Must be <2>, used to represent the number of integer cells in the dma
      property of client devices. The two cells in order are
      1. The first cell represents the channel number.
      2. The second cell is 0 for RX and 1 for TX transfers.
    const: 2

  clocks:
    maxItems: 1

  clock-names:
    const: dma_clk

required:
  - compatible
  - reg
  - interrupts
  - "#dma-cells"
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    dma-controller@ffffec00 {
        compatible = "atmel,at91sam9g45-dma";
        reg = <0xffffec00 0x200>;
        interrupts = <21>;
        #dma-cells = <2>;
        clocks = <&pmc 2 20>;
        clock-names = "dma_clk";
    };

...