Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2024 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/google,gs101-mbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos Mailbox Controller

maintainers:
  - Tudor Ambarus <tudor.ambarus@linaro.org>

description:
  The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16 flag
  bits for hardware interrupt generation and a shared register for passing
  mailbox messages. When the controller is used by the ACPM interface
  the shared register is ignored and the mailbox controller acts as a doorbell.
  The controller just raises the interrupt to the firmware after the
  ACPM interface has written the message to SRAM.

properties:
  compatible:
    const: google,gs101-mbox

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: pclk

  interrupts:
    description: IRQ line for the RX mailbox.
    maxItems: 1

  '#mbox-cells':
    const: 0

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts
  - '#mbox-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/google,gs101.h>

    soc {
        #address-cells = <1>;
        #size-cells = <1>;

        ap2apm_mailbox: mailbox@17610000 {
            compatible = "google,gs101-mbox";
            reg = <0x17610000 0x1000>;
            clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>;
            clock-names = "pclk";
            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>;
            #mbox-cells = <0>;
        };
    };