|  | // SPDX-License-Identifier: GPL-2.0 | 
|  | /* | 
|  | * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car M3-W+ | 
|  | * | 
|  | * Copyright (C) 2020 Renesas Electronics Corp. | 
|  | */ | 
|  |  | 
|  | /dts-v1/; | 
|  | #include "r8a77961.dtsi" | 
|  | #include "ulcb.dtsi" | 
|  |  | 
|  | / { | 
|  | model = "Renesas M3ULCB board based on r8a77961"; | 
|  | compatible = "renesas,m3ulcb", "renesas,r8a77961"; | 
|  |  | 
|  | memory@48000000 { | 
|  | device_type = "memory"; | 
|  | /* first 128MB is reserved for secure area. */ | 
|  | reg = <0x0 0x48000000 0x0 0x78000000>; | 
|  | }; | 
|  |  | 
|  | memory@480000000 { | 
|  | device_type = "memory"; | 
|  | reg = <0x4 0x80000000 0x0 0x80000000>; | 
|  | }; | 
|  |  | 
|  | memory@600000000 { | 
|  | device_type = "memory"; | 
|  | reg = <0x6 0x00000000 0x1 0x00000000>; | 
|  | }; | 
|  | }; | 
|  |  | 
|  | &du { | 
|  | clocks = <&cpg CPG_MOD 724>, | 
|  | <&cpg CPG_MOD 723>, | 
|  | <&cpg CPG_MOD 722>, | 
|  | <&versaclock5 1>, | 
|  | <&versaclock5 3>, | 
|  | <&versaclock5 2>; | 
|  | clock-names = "du.0", "du.1", "du.2", | 
|  | "dclkin.0", "dclkin.1", "dclkin.2"; | 
|  | }; |