| /* SPDX-License-Identifier: GPL-2.0+ */ |
| /* |
| * Copyright 2021 Aspeed Technology Inc. |
| */ |
| #ifndef _ASPEED_ESPI_CTRL_H_ |
| #define _ASPEED_ESPI_CTRL_H_ |
| |
| #include <linux/bits.h> |
| |
| enum aspeed_espi_version { |
| ESPI_AST2500, |
| ESPI_AST2600, |
| }; |
| |
| struct aspeed_espi_model { |
| uint32_t version; |
| }; |
| |
| struct aspeed_espi_ctrl { |
| struct device *dev; |
| |
| struct regmap *map; |
| struct clk *clk; |
| |
| int irq; |
| |
| struct aspeed_espi_perif *perif; |
| struct aspeed_espi_vw *vw; |
| struct aspeed_espi_oob *oob; |
| struct aspeed_espi_flash *flash; |
| |
| const struct aspeed_espi_model *model; |
| }; |
| |
| /* eSPI register offset */ |
| #define ESPI_CTRL 0x000 |
| #define ESPI_CTRL_OOB_RX_SW_RST BIT(28) |
| #define ESPI_CTRL_FLASH_TX_DMA_EN BIT(23) |
| #define ESPI_CTRL_FLASH_RX_DMA_EN BIT(22) |
| #define ESPI_CTRL_OOB_TX_DMA_EN BIT(21) |
| #define ESPI_CTRL_OOB_RX_DMA_EN BIT(20) |
| #define ESPI_CTRL_PERIF_NP_TX_DMA_EN BIT(19) |
| #define ESPI_CTRL_PERIF_PC_TX_DMA_EN BIT(17) |
| #define ESPI_CTRL_PERIF_PC_RX_DMA_EN BIT(16) |
| #define ESPI_CTRL_FLASH_SW_MODE_MASK GENMASK(11, 10) |
| #define ESPI_CTRL_FLASH_SW_MODE_SHIFT 10 |
| #define ESPI_CTRL_PERIF_PC_RX_DMA_EN BIT(16) |
| #define ESPI_CTRL_FLASH_SW_RDY BIT(7) |
| #define ESPI_CTRL_OOB_SW_RDY BIT(4) |
| #define ESPI_CTRL_VW_SW_RDY BIT(3) |
| #define ESPI_CTRL_PERIF_SW_RDY BIT(1) |
| #define ESPI_STS 0x004 |
| #define ESPI_INT_STS 0x008 |
| #define ESPI_INT_STS_HW_RST_DEASSERT BIT(31) |
| #define ESPI_INT_STS_OOB_RX_TMOUT BIT(23) |
| #define ESPI_INT_STS_VW_SYSEVT1 BIT(22) |
| #define ESPI_INT_STS_FLASH_TX_ERR BIT(21) |
| #define ESPI_INT_STS_OOB_TX_ERR BIT(20) |
| #define ESPI_INT_STS_FLASH_TX_ABT BIT(19) |
| #define ESPI_INT_STS_OOB_TX_ABT BIT(18) |
| #define ESPI_INT_STS_PERIF_NP_TX_ABT BIT(17) |
| #define ESPI_INT_STS_PERIF_PC_TX_ABT BIT(16) |
| #define ESPI_INT_STS_FLASH_RX_ABT BIT(15) |
| #define ESPI_INT_STS_OOB_RX_ABT BIT(14) |
| #define ESPI_INT_STS_PERIF_NP_RX_ABT BIT(13) |
| #define ESPI_INT_STS_PERIF_PC_RX_ABT BIT(12) |
| #define ESPI_INT_STS_PERIF_NP_TX_ERR BIT(11) |
| #define ESPI_INT_STS_PERIF_PC_TX_ERR BIT(10) |
| #define ESPI_INT_STS_VW_GPIOEVT BIT(9) |
| #define ESPI_INT_STS_VW_SYSEVT BIT(8) |
| #define ESPI_INT_STS_FLASH_TX_CMPLT BIT(7) |
| #define ESPI_INT_STS_FLASH_RX_CMPLT BIT(6) |
| #define ESPI_INT_STS_OOB_TX_CMPLT BIT(5) |
| #define ESPI_INT_STS_OOB_RX_CMPLT BIT(4) |
| #define ESPI_INT_STS_PERIF_NP_TX_CMPLT BIT(3) |
| #define ESPI_INT_STS_PERIF_PC_TX_CMPLT BIT(1) |
| #define ESPI_INT_STS_PERIF_PC_RX_CMPLT BIT(0) |
| #define ESPI_INT_EN 0x00c |
| #define ESPI_INT_EN_HW_RST_DEASSERT BIT(31) |
| #define ESPI_INT_EN_OOB_RX_TMOUT BIT(23) |
| #define ESPI_INT_EN_VW_SYSEVT1 BIT(22) |
| #define ESPI_INT_EN_FLASH_TX_ERR BIT(21) |
| #define ESPI_INT_EN_OOB_TX_ERR BIT(20) |
| #define ESPI_INT_EN_FLASH_TX_ABT BIT(19) |
| #define ESPI_INT_EN_OOB_TX_ABT BIT(18) |
| #define ESPI_INT_EN_PERIF_NP_TX_ABT BIT(17) |
| #define ESPI_INT_EN_PERIF_PC_TX_ABT BIT(16) |
| #define ESPI_INT_EN_FLASH_RX_ABT BIT(15) |
| #define ESPI_INT_EN_OOB_RX_ABT BIT(14) |
| #define ESPI_INT_EN_PERIF_NP_RX_ABT BIT(13) |
| #define ESPI_INT_EN_PERIF_PC_RX_ABT BIT(12) |
| #define ESPI_INT_EN_PERIF_NP_TX_ERR BIT(11) |
| #define ESPI_INT_EN_PERIF_PC_TX_ERR BIT(10) |
| #define ESPI_INT_EN_VW_GPIOEVT BIT(9) |
| #define ESPI_INT_EN_VW_SYSEVT BIT(8) |
| #define ESPI_INT_EN_FLASH_TX_CMPLT BIT(7) |
| #define ESPI_INT_EN_FLASH_RX_CMPLT BIT(6) |
| #define ESPI_INT_EN_OOB_TX_CMPLT BIT(5) |
| #define ESPI_INT_EN_OOB_RX_CMPLT BIT(4) |
| #define ESPI_INT_EN_PERIF_NP_TX_CMPLT BIT(3) |
| #define ESPI_INT_EN_PERIF_PC_TX_CMPLT BIT(1) |
| #define ESPI_INT_EN_PERIF_PC_RX_CMPLT BIT(0) |
| #define ESPI_PERIF_PC_RX_DMA 0x010 |
| #define ESPI_PERIF_PC_RX_CTRL 0x014 |
| #define ESPI_PERIF_PC_RX_CTRL_PEND_SERV BIT(31) |
| #define ESPI_PERIF_PC_RX_CTRL_LEN_MASK GENMASK(23, 12) |
| #define ESPI_PERIF_PC_RX_CTRL_LEN_SHIFT 12 |
| #define ESPI_PERIF_PC_RX_CTRL_TAG_MASK GENMASK(11, 8) |
| #define ESPI_PERIF_PC_RX_CTRL_TAG_SHIFT 8 |
| #define ESPI_PERIF_PC_RX_CTRL_CYC_MASK GENMASK(7, 0) |
| #define ESPI_PERIF_PC_RX_CTRL_CYC_SHIFT 0 |
| #define ESPI_PERIF_PC_RX_PORT 0x018 |
| #define ESPI_PERIF_PC_TX_DMA 0x020 |
| #define ESPI_PERIF_PC_TX_CTRL 0x024 |
| #define ESPI_PERIF_PC_TX_CTRL_TRIGGER BIT(31) |
| #define ESPI_PERIF_PC_TX_CTRL_LEN_MASK GENMASK(23, 12) |
| #define ESPI_PERIF_PC_TX_CTRL_LEN_SHIFT 12 |
| #define ESPI_PERIF_PC_TX_CTRL_TAG_MASK GENMASK(11, 8) |
| #define ESPI_PERIF_PC_TX_CTRL_TAG_SHIFT 8 |
| #define ESPI_PERIF_PC_TX_CTRL_CYC_MASK GENMASK(7, 0) |
| #define ESPI_PERIF_PC_TX_CTRL_CYC_SHIFT 0 |
| #define ESPI_PERIF_PC_TX_PORT 0x028 |
| #define ESPI_PERIF_NP_TX_DMA 0x030 |
| #define ESPI_PERIF_NP_TX_CTRL 0x034 |
| #define ESPI_PERIF_NP_TX_CTRL_TRIGGER BIT(31) |
| #define ESPI_PERIF_NP_TX_CTRL_LEN_MASK GENMASK(23, 12) |
| #define ESPI_PERIF_NP_TX_CTRL_LEN_SHIFT 12 |
| #define ESPI_PERIF_NP_TX_CTRL_TAG_MASK GENMASK(11, 8) |
| #define ESPI_PERIF_NP_TX_CTRL_TAG_SHIFT 8 |
| #define ESPI_PERIF_NP_TX_CTRL_CYC_MASK GENMASK(7, 0) |
| #define ESPI_PERIF_NP_TX_CTRL_CYC_SHIFT 0 |
| #define ESPI_PERIF_NP_TX_PORT 0x038 |
| #define ESPI_OOB_RX_DMA 0x040 |
| #define ESPI_OOB_RX_CTRL 0x044 |
| #define ESPI_OOB_RX_CTRL_PEND_SERV BIT(31) |
| #define ESPI_OOB_RX_CTRL_LEN_MASK GENMASK(23, 12) |
| #define ESPI_OOB_RX_CTRL_LEN_SHIFT 12 |
| #define ESPI_OOB_RX_CTRL_TAG_MASK GENMASK(11, 8) |
| #define ESPI_OOB_RX_CTRL_TAG_SHIFT 8 |
| #define ESPI_OOB_RX_CTRL_CYC_MASK GENMASK(7, 0) |
| #define ESPI_OOB_RX_CTRL_CYC_SHIFT 0 |
| #define ESPI_OOB_RX_PORT 0x048 |
| #define ESPI_OOB_TX_DMA 0x050 |
| #define ESPI_OOB_TX_CTRL 0x054 |
| #define ESPI_OOB_TX_CTRL_TRIGGER BIT(31) |
| #define ESPI_OOB_TX_CTRL_LEN_MASK GENMASK(23, 12) |
| #define ESPI_OOB_TX_CTRL_LEN_SHIFT 12 |
| #define ESPI_OOB_TX_CTRL_TAG_MASK GENMASK(11, 8) |
| #define ESPI_OOB_TX_CTRL_TAG_SHIFT 8 |
| #define ESPI_OOB_TX_CTRL_CYC_MASK GENMASK(7, 0) |
| #define ESPI_OOB_TX_CTRL_CYC_SHIFT 0 |
| #define ESPI_OOB_TX_PORT 0x058 |
| #define ESPI_FLASH_RX_DMA 0x060 |
| #define ESPI_FLASH_RX_CTRL 0x064 |
| #define ESPI_FLASH_RX_CTRL_PEND_SERV BIT(31) |
| #define ESPI_FLASH_RX_CTRL_LEN_MASK GENMASK(23, 12) |
| #define ESPI_FLASH_RX_CTRL_LEN_SHIFT 12 |
| #define ESPI_FLASH_RX_CTRL_TAG_MASK GENMASK(11, 8) |
| #define ESPI_FLASH_RX_CTRL_TAG_SHIFT 8 |
| #define ESPI_FLASH_RX_CTRL_CYC_MASK GENMASK(7, 0) |
| #define ESPI_FLASH_RX_CTRL_CYC_SHIFT 0 |
| #define ESPI_FLASH_RX_PORT 0x068 |
| #define ESPI_FLASH_TX_DMA 0x070 |
| #define ESPI_FLASH_TX_CTRL 0x074 |
| #define ESPI_FLASH_TX_CTRL_TRIGGER BIT(31) |
| #define ESPI_FLASH_TX_CTRL_LEN_MASK GENMASK(23, 12) |
| #define ESPI_FLASH_TX_CTRL_LEN_SHIFT 12 |
| #define ESPI_FLASH_TX_CTRL_TAG_MASK GENMASK(11, 8) |
| #define ESPI_FLASH_TX_CTRL_TAG_SHIFT 8 |
| #define ESPI_FLASH_TX_CTRL_CYC_MASK GENMASK(7, 0) |
| #define ESPI_FLASH_TX_CTRL_CYC_SHIFT 0 |
| #define ESPI_FLASH_TX_PORT 0x078 |
| #define ESPI_CTRL2 0x080 |
| #define ESPI_CTRL2_MEMCYC_RD_DIS BIT(6) |
| #define ESPI_CTRL2_MEMCYC_WR_DIS BIT(4) |
| #define ESPI_PERIF_PC_RX_SADDR 0x084 |
| #define ESPI_PERIF_PC_RX_TADDR 0x088 |
| #define ESPI_PERIF_PC_RX_MASK 0x08c |
| #define ESPI_PERIF_PC_RX_MASK_CFG_WP BIT(0) |
| #define ESPI_SYSEVT_INT_EN 0x094 |
| #define ESPI_SYSEVT 0x098 |
| #define ESPI_SYSEVT_HOST_RST_ACK BIT(27) |
| #define ESPI_SYSEVT_RST_CPU_INIT BIT(26) |
| #define ESPI_SYSEVT_SLV_BOOT_STS BIT(23) |
| #define ESPI_SYSEVT_NON_FATAL_ERR BIT(22) |
| #define ESPI_SYSEVT_FATAL_ERR BIT(21) |
| #define ESPI_SYSEVT_SLV_BOOT_DONE BIT(20) |
| #define ESPI_SYSEVT_OOB_RST_ACK BIT(16) |
| #define ESPI_SYSEVT_NMI_OUT BIT(10) |
| #define ESPI_SYSEVT_SMI_OUT BIT(9) |
| #define ESPI_SYSEVT_HOST_RST_WARN BIT(8) |
| #define ESPI_SYSEVT_OOB_RST_WARN BIT(6) |
| #define ESPI_SYSEVT_PLTRSTN BIT(5) |
| #define ESPI_SYSEVT_SUSPEND BIT(4) |
| #define ESPI_SYSEVT_S5_SLEEP BIT(2) |
| #define ESPI_SYSEVT_S4_SLEEP BIT(1) |
| #define ESPI_SYSEVT_S3_SLEEP BIT(0) |
| #define ESPI_VW_GPIO_VAL 0x09c |
| #define ESPI_GEN_CAP_N_CONF 0x0a0 |
| #define ESPI_CH0_CAP_N_CONF 0x0a4 |
| #define ESPI_CH1_CAP_N_CONF 0x0a8 |
| #define ESPI_CH2_CAP_N_CONF 0x0ac |
| #define ESPI_CH3_CAP_N_CONF 0x0b0 |
| #define ESPI_CH3_CAP_N_CONF2 0x0b4 |
| #define ESPI_SYSEVT1_INT_EN 0x100 |
| #define ESPI_SYSEVT1 0x104 |
| #define ESPI_SYSEVT1_SUSPEND_ACK BIT(20) |
| #define ESPI_SYSEVT1_SUSPEND_WARN BIT(0) |
| #define ESPI_SYSEVT_INT_T0 0x110 |
| #define ESPI_SYSEVT_INT_T1 0x114 |
| #define ESPI_SYSEVT_INT_T2 0x118 |
| #define ESPI_SYSEVT_INT_T2_HOST_RST_WARN ESPI_SYSEVT_HOST_RST_WARN |
| #define ESPI_SYSEVT_INT_T2_OOB_RST_WARN ESPI_SYSEVT_OOB_RST_WARN |
| #define ESPI_SYSEVT_INT_STS 0x11c |
| #define ESPI_SYSEVT_INT_STS_NMI_OUT ESPI_SYSEVT_NMI_OUT |
| #define ESPI_SYSEVT_INT_STS_SMI_OUT ESPI_SYSEVT_SMI_OUT |
| #define ESPI_SYSEVT_INT_STS_HOST_RST_WARN ESPI_SYSEVT_HOST_RST_WARN |
| #define ESPI_SYSEVT_INT_STS_OOB_RST_WARN ESPI_SYSEVT_OOB_RST_WARN |
| #define ESPI_SYSEVT_INT_STS_PLTRSTN ESPI_SYSEVT_PLTRSTN |
| #define ESPI_SYSEVT_INT_STS_SUSPEND ESPI_SYSEVT_SUSPEND |
| #define ESPI_SYSEVT_INT_STS_S5_SLEEP ESPI_SYSEVT_INT_S5_SLEEP |
| #define ESPI_SYSEVT_INT_STS_S4_SLEEP ESPI_SYSEVT_INT_S4_SLEEP |
| #define ESPI_SYSEVT_INT_STS_S3_SLEEP ESPI_SYSEVT_INT_S3_SLEEP |
| #define ESPI_SYSEVT1_INT_T0 0x120 |
| #define ESPI_SYSEVT1_INT_T1 0x124 |
| #define ESPI_SYSEVT1_INT_T2 0x128 |
| #define ESPI_SYSEVT1_INT_STS 0x12c |
| #define ESPI_SYSEVT1_INT_STS_SUSPEND_WARN ESPI_SYSEVT1_SUSPEND_WARN |
| #define ESPI_OOB_RX_DMA_RB_SIZE 0x130 |
| #define ESPI_OOB_RX_DMA_RD_PTR 0x134 |
| #define ESPI_OOB_RX_DMA_RD_PTR_UPDATE BIT(31) |
| #define ESPI_OOB_RX_DMA_WS_PTR 0x138 |
| #define ESPI_OOB_RX_DMA_WS_PTR_RECV_EN BIT(31) |
| #define ESPI_OOB_RX_DMA_WS_PTR_SP_MASK GENMASK(27, 16) |
| #define ESPI_OOB_RX_DMA_WS_PTR_SP_SHIFT 16 |
| #define ESPI_OOB_RX_DMA_WS_PTR_WP_MASK GENMASK(11, 0) |
| #define ESPI_OOB_RX_DMA_WS_PTR_WP_SHIFT 0 |
| #define ESPI_OOB_TX_DMA_RB_SIZE 0x140 |
| #define ESPI_OOB_TX_DMA_RD_PTR 0x144 |
| #define ESPI_OOB_TX_DMA_RD_PTR_UPDATE BIT(31) |
| #define ESPI_OOB_TX_DMA_WR_PTR 0x148 |
| #define ESPI_OOB_TX_DMA_WR_PTR_SEND_EN BIT(31) |
| |
| /* collect ESPI_INT_STS bits of eSPI channels for convenience */ |
| #define ESPI_INT_STS_PERIF_BITS \ |
| (ESPI_INT_STS_PERIF_NP_TX_ABT | \ |
| ESPI_INT_STS_PERIF_PC_TX_ABT | \ |
| ESPI_INT_STS_PERIF_NP_RX_ABT | \ |
| ESPI_INT_STS_PERIF_PC_RX_ABT | \ |
| ESPI_INT_STS_PERIF_NP_TX_ERR | \ |
| ESPI_INT_STS_PERIF_PC_TX_ERR | \ |
| ESPI_INT_STS_PERIF_NP_TX_CMPLT | \ |
| ESPI_INT_STS_PERIF_PC_TX_CMPLT | \ |
| ESPI_INT_STS_PERIF_PC_RX_CMPLT) |
| |
| #define ESPI_INT_STS_VW_BITS \ |
| (ESPI_INT_STS_VW_SYSEVT1 | \ |
| ESPI_INT_STS_VW_GPIOEVT | \ |
| ESPI_INT_STS_VW_SYSEVT) |
| |
| #define ESPI_INT_STS_OOB_BITS \ |
| (ESPI_INT_STS_OOB_RX_TMOUT | \ |
| ESPI_INT_STS_OOB_TX_ERR | \ |
| ESPI_INT_STS_OOB_TX_ABT | \ |
| ESPI_INT_STS_OOB_RX_ABT | \ |
| ESPI_INT_STS_OOB_TX_CMPLT | \ |
| ESPI_INT_STS_OOB_RX_CMPLT) |
| |
| #define ESPI_INT_STS_FLASH_BITS \ |
| (ESPI_INT_STS_FLASH_TX_ERR | \ |
| ESPI_INT_STS_FLASH_TX_ABT | \ |
| ESPI_INT_STS_FLASH_RX_ABT | \ |
| ESPI_INT_STS_FLASH_TX_CMPLT | \ |
| ESPI_INT_STS_FLASH_RX_CMPLT) |
| |
| /* collect ESPI_INT_EN bits of eSPI channels for convenience */ |
| #define ESPI_INT_EN_PERIF_BITS \ |
| (ESPI_INT_EN_PERIF_NP_TX_ABT | \ |
| ESPI_INT_EN_PERIF_PC_TX_ABT | \ |
| ESPI_INT_EN_PERIF_NP_RX_ABT | \ |
| ESPI_INT_EN_PERIF_PC_RX_ABT | \ |
| ESPI_INT_EN_PERIF_NP_TX_ERR | \ |
| ESPI_INT_EN_PERIF_PC_TX_ERR | \ |
| ESPI_INT_EN_PERIF_NP_TX_CMPLT | \ |
| ESPI_INT_EN_PERIF_PC_TX_CMPLT | \ |
| ESPI_INT_EN_PERIF_PC_RX_CMPLT) |
| |
| #define ESPI_INT_EN_VW_BITS \ |
| (ESPI_INT_EN_VW_SYSEVT1 | \ |
| ESPI_INT_EN_VW_GPIOEVT | \ |
| ESPI_INT_EN_VW_SYSEVT) |
| |
| #define ESPI_INT_EN_OOB_BITS \ |
| (ESPI_INT_EN_OOB_RX_TMOUT | \ |
| ESPI_INT_EN_OOB_TX_ERR | \ |
| ESPI_INT_EN_OOB_TX_ABT | \ |
| ESPI_INT_EN_OOB_RX_ABT | \ |
| ESPI_INT_EN_OOB_TX_CMPLT | \ |
| ESPI_INT_EN_OOB_RX_CMPLT) |
| |
| #define ESPI_INT_EN_FLASH_BITS \ |
| (ESPI_INT_EN_FLASH_TX_ERR | \ |
| ESPI_INT_EN_FLASH_TX_ABT | \ |
| ESPI_INT_EN_FLASH_RX_ABT | \ |
| ESPI_INT_EN_FLASH_TX_CMPLT | \ |
| ESPI_INT_EN_FLASH_RX_CMPLT) |
| |
| #endif |
